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[2001:4c4e:24ed:fa00:ace5:6db4:a62d:1e35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490e2ca1a43sm128071305e9.8.2026.06.11.23.13.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 23:13:03 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: natalie.vock@gmx.de, honghuan@amd.com, Alexander.Deucher@amd.com, Felix.Kuehling@amd.com, Philip.Yang@amd.com, christian.koenig@amd.com Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 02/13] drm/amdgpu: give different sizes for each SA pool type Date: Fri, 12 Jun 2026 08:13:02 +0200 Message-ID: <2796234.vuYhMxLoTh@timur-max> In-Reply-To: <20260529114031.3714-3-christian.koenig@amd.com> References: <20260529114031.3714-1-christian.koenig@amd.com> <20260529114031.3714-3-christian.koenig@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. m=C3=A1jus 29., p=C3=A9ntek 13:24:04 k=C3=B6z=C3=A9p-eur=C3=B3pai = ny=C3=A1ri id=C5=91 Christian K=C3=B6nig=20 wrote: > The IMMEDIATE (page fault) and DIRECT (reset) pool should be used only > very rarely and by a single thread. >=20 > Saves roughly 1.25MiB of memory and GART space for each amdgpu device. >=20 > Signed-off-by: Christian K=C3=B6nig > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 8 +++++++- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 -- > 2 files changed, 7 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index f1ed4a436f5b..334f95f8f339 > 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > @@ -351,14 +351,20 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, > unsigned int num_ibs, */ > int amdgpu_ib_pool_init(struct amdgpu_device *adev) > { > + const int sizes[AMDGPU_IB_POOL_MAX] =3D { > + [AMDGPU_IB_POOL_DELAYED] =3D SZ_1M, > + [AMDGPU_IB_POOL_IMMEDIATE] =3D SZ_128K, > + [AMDGPU_IB_POOL_DIRECT] =3D SZ_512K > + }; > int r, i; >=20 > if (adev->ib_pool_ready) > return 0; >=20 > + There is a spurious newline here. Otherwise the patch makes good sense. Reviewed-by: Timur Krist=C3=B3f > for (i =3D 0; i < AMDGPU_IB_POOL_MAX; i++) { > r =3D amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i], > - =20 AMDGPU_IB_POOL_SIZE, 256, > + sizes[i], 256, > =20 AMDGPU_GEM_DOMAIN_GTT); > if (r) > goto error; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 8f28b3bd7010..1a063a0a42= 80 > 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > @@ -68,8 +68,6 @@ enum amdgpu_ring_priority_level { >=20 > #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) >=20 > -#define AMDGPU_IB_POOL_SIZE (1024 * 1024) > - > enum amdgpu_ring_type { > AMDGPU_RING_TYPE_GFX =3D AMDGPU_HW_IP_GFX, > AMDGPU_RING_TYPE_COMPUTE =3D AMDGPU_HW_IP_COMPUTE,