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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id z12-20020a056870e14c00b0016e8726f0d4sm4903995oaa.3.2023.05.08.05.44.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 May 2023 05:44:30 -0700 (PDT) Message-ID: <27f0bafe-2a17-d64c-e749-047c0a12d083@ventanamicro.com> Date: Mon, 8 May 2023 09:44:27 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH 06/11] tcg/riscv: Support rotates from Zbb Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20230503085657.1814850-1-richard.henderson@linaro.org> <20230503085657.1814850-7-richard.henderson@linaro.org> From: Daniel Henrique Barboza In-Reply-To: <20230503085657.1814850-7-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -38 X-Spam_score: -3.9 X-Spam_bar: --- X-Spam_report: (-3.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.802, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/3/23 05:56, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- Reviewed-by: Daniel Henrique Barboza > tcg/riscv/tcg-target.h | 4 ++-- > tcg/riscv/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++ > 2 files changed, 36 insertions(+), 2 deletions(-) > > diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h > index 9f58d46208..317d385924 100644 > --- a/tcg/riscv/tcg-target.h > +++ b/tcg/riscv/tcg-target.h > @@ -101,7 +101,7 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_div_i32 1 > #define TCG_TARGET_HAS_rem_i32 1 > #define TCG_TARGET_HAS_div2_i32 0 > -#define TCG_TARGET_HAS_rot_i32 0 > +#define TCG_TARGET_HAS_rot_i32 have_zbb > #define TCG_TARGET_HAS_deposit_i32 0 > #define TCG_TARGET_HAS_extract_i32 0 > #define TCG_TARGET_HAS_sextract_i32 0 > @@ -136,7 +136,7 @@ extern bool have_zbb; > #define TCG_TARGET_HAS_div_i64 1 > #define TCG_TARGET_HAS_rem_i64 1 > #define TCG_TARGET_HAS_div2_i64 0 > -#define TCG_TARGET_HAS_rot_i64 0 > +#define TCG_TARGET_HAS_rot_i64 have_zbb > #define TCG_TARGET_HAS_deposit_i64 0 > #define TCG_TARGET_HAS_extract_i64 0 > #define TCG_TARGET_HAS_sextract_i64 0 > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index f64eaa8515..58f969b4fe 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1458,6 +1458,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > > + case INDEX_op_rotl_i32: > + if (c2) { > + tcg_out_opc_imm(s, OPC_RORIW, a0, a1, -a2 & 0x1f); > + } else { > + tcg_out_opc_reg(s, OPC_ROLW, a0, a1, a2); > + } > + break; > + case INDEX_op_rotl_i64: > + if (c2) { > + tcg_out_opc_imm(s, OPC_RORI, a0, a1, -a2 & 0x3f); > + } else { > + tcg_out_opc_reg(s, OPC_ROL, a0, a1, a2); > + } > + break; > + > + case INDEX_op_rotr_i32: > + if (c2) { > + tcg_out_opc_imm(s, OPC_RORIW, a0, a1, a2 & 0x1f); > + } else { > + tcg_out_opc_reg(s, OPC_RORW, a0, a1, a2); > + } > + break; > + case INDEX_op_rotr_i64: > + if (c2) { > + tcg_out_opc_imm(s, OPC_RORI, a0, a1, a2 & 0x3f); > + } else { > + tcg_out_opc_reg(s, OPC_ROR, a0, a1, a2); > + } > + break; > + > case INDEX_op_add2_i32: > tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], > const_args[4], const_args[5], false, true); > @@ -1629,9 +1659,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) > case INDEX_op_shl_i32: > case INDEX_op_shr_i32: > case INDEX_op_sar_i32: > + case INDEX_op_rotl_i32: > + case INDEX_op_rotr_i32: > case INDEX_op_shl_i64: > case INDEX_op_shr_i64: > case INDEX_op_sar_i64: > + case INDEX_op_rotl_i64: > + case INDEX_op_rotr_i64: > return C_O1_I2(r, r, ri); > > case INDEX_op_brcond_i32: