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[2001:4c4e:24ef:f00:8016:2cdb:5b2d:facf]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-477ddf0fb15sm6300861f8f.29.2026.07.02.02.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2026 02:14:56 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Alexander.Deucher@amd.com, Natalie Vock , Amir Shetaia , Marek =?UTF-8?B?T2zFocOhaw==?= , Mario Limonciello , Tvrtko Ursulin , Felix Kuehling , Lijo Lazar , Siwei He , Philip Yang , Mukul Joshi , Christian =?UTF-8?B?S8O2bmln?= Subject: Re: [PATCH 02/14] drm/amdgpu/gfxhub: Enable retry fault interrupts when needed Date: Thu, 02 Jul 2026 11:14:53 +0200 Message-ID: <2821958.vuYhMxLoTh@timur-max> In-Reply-To: References: <20260701161721.85681-1-timur.kristof@gmail.com> <20260701161721.85681-3-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. j=C3=BAlius 2., cs=C3=BCt=C3=B6rt=C3=B6k 10:10:10 k=C3=B6z=C3=A9p-= eur=C3=B3pai ny=C3=A1ri id=C5=91 Christian K=C3=B6nig=20 wrote: > On 7/1/26 18:17, Timur Krist=C3=B3f wrote: > > Enable retry fault interrupts when initializing the GFXHUB > > system aperture registers according to whether retrying > > page faults is enabled in amdgpu (ie. amdgpu.noretry=3D0). > >=20 > > Needs to be done for each GFXHUB version at once, > > because none of them actually enabled this interrupt. >=20 > Thinking more about it we are clearly missing something here. The retry > fault interrupt itself should be enabled all the time. Why would it be enabled all the time? I haven't seen any retry faults on neither Navi 3 nor Navi 4 without enabli= ng=20 the ENABLE_RETRY_FAULT_INTERRUPT bit. >=20 > IIRC only the RETRY_PERMISSION_OR_INVALID_PAGE_FAULT bit in the > VM_CONTEXT0_CNTL register should be set or cleared by the kernel driver or > firmware to control if the HW retries the access or not. That is clearly not the case on GFX12.1 and I haven't seen any indication t= hat=20 it would be different on GFX11.x and 12.0 either. > > --- > >=20 > > drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 2 ++ > > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 9 +++++++-- > > 8 files changed, 51 insertions(+), 14 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c index > > 652eea6eae4a..ef20eafd59ae 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > > @@ -155,6 +155,7 @@ static void > > gfxhub_v11_5_0_init_gart_aperture_regs(struct amdgpu_device *adev)>=20 > > static void gfxhub_v11_5_0_init_system_aperture_regs(struct amdgpu_dev= ice > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); > > WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >>=20 24); > >=20 > > @@ -180,8 +181,12 @@ static void > > gfxhub_v11_5_0_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > } > > =20 > > static void gfxhub_v11_5_0_init_tlb_regs(struct amdgpu_device *adev) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c index > > 6cbf837d50dd..ec3ff4dec674 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c > > @@ -158,6 +158,7 @@ static void > > gfxhub_v12_0_init_gart_aperture_regs(struct amdgpu_device *adev)>=20 > > static void gfxhub_v12_0_init_system_aperture_regs(struct amdgpu_device > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > /* Program the AGP BAR */ > > WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); > >=20 > > @@ -184,8 +185,12 @@ static void > > gfxhub_v12_0_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > } > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index > > bfe247b1a333..27d7f7cb903f 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > > @@ -91,6 +91,7 @@ static void gfxhub_v1_0_init_gart_aperture_regs(struct > > amdgpu_device *adev)>=20 > > static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > if (!amdgpu_sriov_vf(adev) || adev->asic_type <=3D CHIP_VEGA10) { > > =09 > > /* Program the AGP BAR */ > >=20 > > @@ -134,8 +135,12 @@ static void > > gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0,=20 mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >>=20 44)); > >=20 > > - WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY,=20 1); > > + tmp =3D RREG32_SOC15(GC, 0,=20 mmVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ENABLE_RETRY_FAULT_INTERRUPT, !adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2,=20 tmp); > >=20 > > } > > =09 > > /* In the case squeezing vram into GART aperture, we don't use > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c index > > fbdf46070b38..ed9a64bc5aaa 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > > @@ -176,6 +176,8 @@ gfxhub_v1_2_xcc_init_system_aperture_regs(struct > > amdgpu_device *adev,>=20 > > tmp =3D RREG32_SOC15(GC, GET_INST(GC, i), > > regVM_L2_PROTECTION_FAULT_CNTL2); > > tmp =3D REG_SET_FIELD(tmp,=20 VM_L2_PROTECTION_FAULT_CNTL2, > > =09 > > =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > >=20 > > + tmp =3D REG_SET_FIELD(tmp,=20 VM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ENABLE_RETRY_FAULT_INTERRUPT, !adev->gmc.noretry); > >=20 > > WREG32_SOC15(GC, GET_INST(GC, i),=20 regVM_L2_PROTECTION_FAULT_CNTL2, > > tmp); > > =09 > > } > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c index > > 9ea593e2c719..152b2735d360 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > > @@ -151,6 +151,7 @@ static void gfxhub_v2_0_init_gart_aperture_regs(str= uct > > amdgpu_device *adev)>=20 > > static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > if (!amdgpu_sriov_vf(adev)) { > > =09 > > /* Program the AGP BAR */ > >=20 > > @@ -178,8 +179,12 @@ static void > > gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > } > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c index > > 30b90d35abd0..83c2ddbbd292 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > > @@ -154,6 +154,7 @@ static void gfxhub_v2_1_init_gart_aperture_regs(str= uct > > amdgpu_device *adev)>=20 > > static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > if (amdgpu_sriov_vf(adev)) > > =09 > > return; > >=20 > > @@ -182,8 +183,12 @@ static void > > gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > } > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c index > > 9e6a6e13dec0..90bbb2fe4884 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > > @@ -150,6 +150,7 @@ static void gfxhub_v3_0_init_gart_aperture_regs(str= uct > > amdgpu_device *adev)>=20 > > static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > /* Program the AGP BAR */ > > WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); > >=20 > > @@ -176,8 +177,12 @@ static void > > gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > } > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c index > > b3b1085c7cd3..1b3c067ab48c 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > > @@ -153,6 +153,7 @@ static void > > gfxhub_v3_0_3_init_gart_aperture_regs(struct amdgpu_device *adev)>=20 > > static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_devi= ce > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > if (amdgpu_sriov_vf(adev)) > > =09 > > return; > >=20 > > @@ -181,8 +182,12 @@ static void > > gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > }