From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 053E4271456; Sat, 1 Aug 2026 16:28:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785601730; cv=none; b=gb8kRJ9oPNU7JJhoG56E51ueIwAt6O7vcC1JLveinx1sAjLgL+eFuQsVIQPUUJ/KS0R7FKqxMPExx3MCuyHwsCPYiMo56VzP3Ou87exQZbR5PkrX4LBEumlgOdFiNSSyOEiJMLYBE/he/SUU98TMDim47Is8l5TdKlYRMQNGsnE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785601730; c=relaxed/simple; bh=IkVjWSBBiuOLsbPEFfnehNUTyZsRPGGxxctkNh5DZAU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ttnz6mCExjYd5BE8upRGfqDNOQzAPMrMUGzVmGi+Oghk3teRC0oog+eDAAD2w3XrXNUhzKVqCxd8+RGjwgYC6oPj4q6DayyUHkOifRO2ePT/NFRhr0QFs+cdFAr1wT3S7CA5lOn4tmsBp93yDr7feHGD0hFpD6fI01mtFcCp7zU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=GkspQDxI; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="GkspQDxI" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=V06eygovF9pqY3vHyXKEpDH3PhLpNuC5Yjsi32fVPNY=; b=GkspQDxIH8XQuNGEPi3OaHsWVb MWqmQLy8kUKXVbYdQCn+ie/STVzV3V1s7aPOK5PK5RjrA5Wiyz8hXdbdIEgc6WcPFfAa21KBC40+n tiyw0Mn+j6oxgkEwMCeuve4BVeBfqLtB2EPeZ7wTyUU4mSmU1sLPii9wSHsjQ5BuPbhAuQtRTEjA5 n8pZMtkAH/FxaT++U1I8L6londMFmfOBCEtEEp2HcNsc6P3S1esk+oUHFDqac/TtiB/qTngEgeWVx vxh6+0AgQRrVMtC7TkoRzlWwcomWycXXPeveXnhe6HMtGaMMJNgHU/uwXIYS2D1qggPlKOWmYdUmd HqiZeHug==; From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2 05/10] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes Date: Sat, 01 Aug 2026 18:28:11 +0200 Message-ID: <2847036.GUH7pLUipS@diego> In-Reply-To: <20260801142244.679437-7-coiaprant@gmail.com> References: <20260801142244.679437-2-coiaprant@gmail.com> <20260801142244.679437-7-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Samstag, 1. August 2026, 16:22:29 Mitteleurop=C3=A4ische Sommerzeit schr= ieb Coia Prant: > The RK3568 SoC integrates a Synopsys DesignWare XPCS that provides > the Physical Coding Sublayer for 1000BASE-X, SGMII, and QSGMII > interfaces via its four MII ports. Add the XPCS device node and > its pcs-mii sub-nodes to the SoC device tree. >=20 > The XPCS device is accessed via the APB3 bus at 0xfda00000 and > requires the CSR clock (PCLK_XPCS) for register access and the EEE > clock (CLK_XPCS_EEE) for Energy Efficient Ethernet operation. The > PD_PIPE power domain must be enabled before any register access. >=20 > Also add two fixed-clock nodes (xpcs_gmac0_clk and xpcs_gmac1_clk) > providing the 125 MHz reference clock for the GMACs when operating > with XPCS. These clocks are used as the assigned-clock-parents > for the respective GMAC nodes in board-level device trees. >=20 > The XPCS node and its pcs-mii sub-nodes are disabled by default and > must be enabled at the board level when 1000BASE-X/SGMII/QSGMII is > in use. The fixed-clock nodes are always present and do not have a > status property, as they are static clock sources. >=20 > The XPCS node also requires a reference to the appropriate Naneng > Combo PHY via the phys property at the board level. >=20 > Signed-off-by: Coia Prant > --- > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 45 ++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/d= ts/rockchip/rk3568.dtsi > index 3bc653f027f1f..989e164c0eb39 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > @@ -110,6 +110,51 @@ sata0: sata@fc000000 { > status =3D "disabled"; > }; > =20 > + xpcs: pcs@fda00000 { > + compatible =3D "rockchip,rk3568-xpcs"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + reg =3D <0x0 0xfda00000 0x0 0x200000>; > + clocks =3D <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; > + clock-names =3D "csr", "eee"; > + power-domains =3D <&power RK3568_PD_PIPE>; > + status =3D "disabled"; > + > + xpcs_mii0: pcs-mii@0 { > + reg =3D <0>; > + status =3D "disabled"; > + }; > + > + xpcs_mii1: pcs-mii@1 { > + reg =3D <1>; > + status =3D "disabled"; > + }; > + > + xpcs_mii2: pcs-mii@2 { > + reg =3D <2>; > + status =3D "disabled"; > + }; > + > + xpcs_mii3: pcs-mii@3 { > + reg =3D <3>; > + status =3D "disabled"; > + }; > + }; > + > + xpcs_gmac0_clk: xpcs-gmac0-clock { > + compatible =3D "fixed-clock"; > + clock-frequency =3D <125000000>; > + clock-output-names =3D "clk_gmac0_xpcs_mii"; > + #clock-cells =3D <0>; > + }; > + > + xpcs_gmac1_clk: xpcs-gmac1-clock { > + compatible =3D "fixed-clock"; > + clock-frequency =3D <125000000>; > + clock-output-names =3D "clk_gmac1_xpcs_mii"; > + #clock-cells =3D <0>; > + }; I don't fully believe those clocks are "just there" inside the SoC. Instead I _assume_ they are generated by some oscillator on the individual boards? Because as described there, they would be just magically be there. So please aim for a real clock description (likely on a board-level) Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D89D4C55173 for ; Sat, 1 Aug 2026 16:28:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=R8WUXF2sC94fpQrQT9/tGcAim9oC1MXs4wwuWJEfOe4=; b=mBtphdIcuwHEqb HPDnT4QVN/8KzKUWbJ7YxzO3i0Js/DKLvl6yc2czJYXb92grC70RRmM1vYF7qEJ//lDiY/24ZCpQl RHJoZaLaE8oJxfuUkLY9jCLhX0Wbm9725FmhnBqlrex7WpbjmBcDFxxkAdOITRU2WJLioOrZWTy7S G1P+DWc37goyRv38rXT9NrN/U8Ftp0QUuwBdqAmffXGqw04pp0ZsTheU/lxnszfPkhvMsqw6C6fKM MQJo65dTmvkK1lhTCgaxnZSJSc5tlT44jF+GdoKMsoCGQfFhRUrBtbsppSYtVNm7PRQiIlUHgmUt7 iJkeW+IOq0lvHoCTcRWg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wqCZm-0000000ErSq-1ObH; Sat, 01 Aug 2026 16:28:42 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wqCZj-0000000ErS1-0bSp; Sat, 01 Aug 2026 16:28:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=V06eygovF9pqY3vHyXKEpDH3PhLpNuC5Yjsi32fVPNY=; b=GkspQDxIH8XQuNGEPi3OaHsWVb MWqmQLy8kUKXVbYdQCn+ie/STVzV3V1s7aPOK5PK5RjrA5Wiyz8hXdbdIEgc6WcPFfAa21KBC40+n tiyw0Mn+j6oxgkEwMCeuve4BVeBfqLtB2EPeZ7wTyUU4mSmU1sLPii9wSHsjQ5BuPbhAuQtRTEjA5 n8pZMtkAH/FxaT++U1I8L6londMFmfOBCEtEEp2HcNsc6P3S1esk+oUHFDqac/TtiB/qTngEgeWVx vxh6+0AgQRrVMtC7TkoRzlWwcomWycXXPeveXnhe6HMtGaMMJNgHU/uwXIYS2D1qggPlKOWmYdUmd HqiZeHug==; From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2 05/10] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes Date: Sat, 01 Aug 2026 18:28:11 +0200 Message-ID: <2847036.GUH7pLUipS@diego> In-Reply-To: <20260801142244.679437-7-coiaprant@gmail.com> References: <20260801142244.679437-2-coiaprant@gmail.com> <20260801142244.679437-7-coiaprant@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260801_092839_215141_5A762A9C X-CRM114-Status: GOOD ( 18.07 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org QW0gU2Ftc3RhZywgMS4gQXVndXN0IDIwMjYsIDE2OjIyOjI5IE1pdHRlbGV1cm9ww6Rpc2NoZSBT b21tZXJ6ZWl0IHNjaHJpZWIgQ29pYSBQcmFudDoKPiBUaGUgUkszNTY4IFNvQyBpbnRlZ3JhdGVz IGEgU3lub3BzeXMgRGVzaWduV2FyZSBYUENTIHRoYXQgcHJvdmlkZXMKPiB0aGUgUGh5c2ljYWwg Q29kaW5nIFN1YmxheWVyIGZvciAxMDAwQkFTRS1YLCBTR01JSSwgYW5kIFFTR01JSQo+IGludGVy ZmFjZXMgdmlhIGl0cyBmb3VyIE1JSSBwb3J0cy4gIEFkZCB0aGUgWFBDUyBkZXZpY2Ugbm9kZSBh bmQKPiBpdHMgcGNzLW1paSBzdWItbm9kZXMgdG8gdGhlIFNvQyBkZXZpY2UgdHJlZS4KPiAKPiBU aGUgWFBDUyBkZXZpY2UgaXMgYWNjZXNzZWQgdmlhIHRoZSBBUEIzIGJ1cyBhdCAweGZkYTAwMDAw IGFuZAo+IHJlcXVpcmVzIHRoZSBDU1IgY2xvY2sgKFBDTEtfWFBDUykgZm9yIHJlZ2lzdGVyIGFj Y2VzcyBhbmQgdGhlIEVFRQo+IGNsb2NrIChDTEtfWFBDU19FRUUpIGZvciBFbmVyZ3kgRWZmaWNp ZW50IEV0aGVybmV0IG9wZXJhdGlvbi4gIFRoZQo+IFBEX1BJUEUgcG93ZXIgZG9tYWluIG11c3Qg YmUgZW5hYmxlZCBiZWZvcmUgYW55IHJlZ2lzdGVyIGFjY2Vzcy4KPiAKPiBBbHNvIGFkZCB0d28g Zml4ZWQtY2xvY2sgbm9kZXMgKHhwY3NfZ21hYzBfY2xrIGFuZCB4cGNzX2dtYWMxX2NsaykKPiBw cm92aWRpbmcgdGhlIDEyNSBNSHogcmVmZXJlbmNlIGNsb2NrIGZvciB0aGUgR01BQ3Mgd2hlbiBv cGVyYXRpbmcKPiB3aXRoIFhQQ1MuICBUaGVzZSBjbG9ja3MgYXJlIHVzZWQgYXMgdGhlIGFzc2ln bmVkLWNsb2NrLXBhcmVudHMKPiBmb3IgdGhlIHJlc3BlY3RpdmUgR01BQyBub2RlcyBpbiBib2Fy ZC1sZXZlbCBkZXZpY2UgdHJlZXMuCj4gCj4gVGhlIFhQQ1Mgbm9kZSBhbmQgaXRzIHBjcy1taWkg c3ViLW5vZGVzIGFyZSBkaXNhYmxlZCBieSBkZWZhdWx0IGFuZAo+IG11c3QgYmUgZW5hYmxlZCBh dCB0aGUgYm9hcmQgbGV2ZWwgd2hlbiAxMDAwQkFTRS1YL1NHTUlJL1FTR01JSSBpcwo+IGluIHVz ZS4gIFRoZSBmaXhlZC1jbG9jayBub2RlcyBhcmUgYWx3YXlzIHByZXNlbnQgYW5kIGRvIG5vdCBo YXZlIGEKPiBzdGF0dXMgcHJvcGVydHksIGFzIHRoZXkgYXJlIHN0YXRpYyBjbG9jayBzb3VyY2Vz Lgo+IAo+IFRoZSBYUENTIG5vZGUgYWxzbyByZXF1aXJlcyBhIHJlZmVyZW5jZSB0byB0aGUgYXBw cm9wcmlhdGUgTmFuZW5nCj4gQ29tYm8gUEhZIHZpYSB0aGUgcGh5cyBwcm9wZXJ0eSBhdCB0aGUg Ym9hcmQgbGV2ZWwuCj4gCj4gU2lnbmVkLW9mZi1ieTogQ29pYSBQcmFudCA8Y29pYXByYW50QGdt YWlsLmNvbT4KPiAtLS0KPiAgYXJjaC9hcm02NC9ib290L2R0cy9yb2NrY2hpcC9yazM1NjguZHRz aSB8IDQ1ICsrKysrKysrKysrKysrKysrKysrKysrKwo+ICAxIGZpbGUgY2hhbmdlZCwgNDUgaW5z ZXJ0aW9ucygrKQo+IAo+IGRpZmYgLS1naXQgYS9hcmNoL2FybTY0L2Jvb3QvZHRzL3JvY2tjaGlw L3JrMzU2OC5kdHNpIGIvYXJjaC9hcm02NC9ib290L2R0cy9yb2NrY2hpcC9yazM1NjguZHRzaQo+ IGluZGV4IDNiYzY1M2YwMjdmMWYuLjk4OWUxNjRjMGViMzkgMTAwNjQ0Cj4gLS0tIGEvYXJjaC9h cm02NC9ib290L2R0cy9yb2NrY2hpcC9yazM1NjguZHRzaQo+ICsrKyBiL2FyY2gvYXJtNjQvYm9v dC9kdHMvcm9ja2NoaXAvcmszNTY4LmR0c2kKPiBAQCAtMTEwLDYgKzExMCw1MSBAQCBzYXRhMDog c2F0YUBmYzAwMDAwMCB7Cj4gIAkJc3RhdHVzID0gImRpc2FibGVkIjsKPiAgCX07Cj4gIAo+ICsJ eHBjczogcGNzQGZkYTAwMDAwIHsKPiArCQljb21wYXRpYmxlID0gInJvY2tjaGlwLHJrMzU2OC14 cGNzIjsKPiArCQkjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiArCQkjc2l6ZS1jZWxscyA9IDwwPjsK PiArCQlyZWcgPSA8MHgwIDB4ZmRhMDAwMDAgMHgwIDB4MjAwMDAwPjsKPiArCQljbG9ja3MgPSA8 JmNydSBQQ0xLX1hQQ1M+LCA8JmNydSBDTEtfWFBDU19FRUU+Owo+ICsJCWNsb2NrLW5hbWVzID0g ImNzciIsICJlZWUiOwo+ICsJCXBvd2VyLWRvbWFpbnMgPSA8JnBvd2VyIFJLMzU2OF9QRF9QSVBF PjsKPiArCQlzdGF0dXMgPSAiZGlzYWJsZWQiOwo+ICsKPiArCQl4cGNzX21paTA6IHBjcy1taWlA MCB7Cj4gKwkJCXJlZyA9IDwwPjsKPiArCQkJc3RhdHVzID0gImRpc2FibGVkIjsKPiArCQl9Owo+ ICsKPiArCQl4cGNzX21paTE6IHBjcy1taWlAMSB7Cj4gKwkJCXJlZyA9IDwxPjsKPiArCQkJc3Rh dHVzID0gImRpc2FibGVkIjsKPiArCQl9Owo+ICsKPiArCQl4cGNzX21paTI6IHBjcy1taWlAMiB7 Cj4gKwkJCXJlZyA9IDwyPjsKPiArCQkJc3RhdHVzID0gImRpc2FibGVkIjsKPiArCQl9Owo+ICsK PiArCQl4cGNzX21paTM6IHBjcy1taWlAMyB7Cj4gKwkJCXJlZyA9IDwzPjsKPiArCQkJc3RhdHVz ID0gImRpc2FibGVkIjsKPiArCQl9Owo+ICsJfTsKPiArCj4gKwl4cGNzX2dtYWMwX2NsazogeHBj cy1nbWFjMC1jbG9jayB7Cj4gKwkJY29tcGF0aWJsZSA9ICJmaXhlZC1jbG9jayI7Cj4gKwkJY2xv Y2stZnJlcXVlbmN5ID0gPDEyNTAwMDAwMD47Cj4gKwkJY2xvY2stb3V0cHV0LW5hbWVzID0gImNs a19nbWFjMF94cGNzX21paSI7Cj4gKwkJI2Nsb2NrLWNlbGxzID0gPDA+Owo+ICsJfTsKPiArCj4g Kwl4cGNzX2dtYWMxX2NsazogeHBjcy1nbWFjMS1jbG9jayB7Cj4gKwkJY29tcGF0aWJsZSA9ICJm aXhlZC1jbG9jayI7Cj4gKwkJY2xvY2stZnJlcXVlbmN5ID0gPDEyNTAwMDAwMD47Cj4gKwkJY2xv Y2stb3V0cHV0LW5hbWVzID0gImNsa19nbWFjMV94cGNzX21paSI7Cj4gKwkJI2Nsb2NrLWNlbGxz ID0gPDA+Owo+ICsJfTsKCkkgZG9uJ3QgZnVsbHkgYmVsaWV2ZSB0aG9zZSBjbG9ja3MgYXJlICJq dXN0IHRoZXJlIiBpbnNpZGUgdGhlIFNvQy4KSW5zdGVhZCBJIF9hc3N1bWVfIHRoZXkgYXJlIGdl bmVyYXRlZCBieSBzb21lIG9zY2lsbGF0b3Igb24gdGhlCmluZGl2aWR1YWwgYm9hcmRzPwoKQmVj YXVzZSBhcyBkZXNjcmliZWQgdGhlcmUsIHRoZXkgd291bGQgYmUganVzdCBtYWdpY2FsbHkgYmUg dGhlcmUuCgpTbyBwbGVhc2UgYWltIGZvciBhIHJlYWwgY2xvY2sgZGVzY3JpcHRpb24gKGxpa2Vs eSBvbiBhIGJvYXJkLWxldmVsKQoKCkhlaWtvCgoKCgotLSAKbGludXgtcGh5IG1haWxpbmcgbGlz dApsaW51eC1waHlAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwczovL2xpc3RzLmluZnJhZGVhZC5v cmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1waHkK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC793C55173 for ; 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Sat, 01 Aug 2026 16:28:42 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wqCZj-0000000ErS1-0bSp; Sat, 01 Aug 2026 16:28:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=V06eygovF9pqY3vHyXKEpDH3PhLpNuC5Yjsi32fVPNY=; b=GkspQDxIH8XQuNGEPi3OaHsWVb MWqmQLy8kUKXVbYdQCn+ie/STVzV3V1s7aPOK5PK5RjrA5Wiyz8hXdbdIEgc6WcPFfAa21KBC40+n tiyw0Mn+j6oxgkEwMCeuve4BVeBfqLtB2EPeZ7wTyUU4mSmU1sLPii9wSHsjQ5BuPbhAuQtRTEjA5 n8pZMtkAH/FxaT++U1I8L6londMFmfOBCEtEEp2HcNsc6P3S1esk+oUHFDqac/TtiB/qTngEgeWVx vxh6+0AgQRrVMtC7TkoRzlWwcomWycXXPeveXnhe6HMtGaMMJNgHU/uwXIYS2D1qggPlKOWmYdUmd HqiZeHug==; From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2 05/10] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes Date: Sat, 01 Aug 2026 18:28:11 +0200 Message-ID: <2847036.GUH7pLUipS@diego> In-Reply-To: <20260801142244.679437-7-coiaprant@gmail.com> References: <20260801142244.679437-2-coiaprant@gmail.com> <20260801142244.679437-7-coiaprant@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260801_092839_215141_5A762A9C X-CRM114-Status: GOOD ( 18.07 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; 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