From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: linux-sh@vger.kernel.org
Subject: Re: [PATCH] irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
Date: Tue, 12 Nov 2013 13:22:28 +0000 [thread overview]
Message-ID: <2947619.amuqD9kmbv@avalon> (raw)
In-Reply-To: <1383999481-2742-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
Hi Magnus,
On Tuesday 12 November 2013 14:44:13 Magnus Damm wrote:
> On Sat, Nov 9, 2013 at 9:18 PM, Laurent Pinchart wrote:
> > The SENSE register bitfield position is incorrectly computed for SoCs
> > that use 2-bit IRQ sense fields. Fix it.
> >
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com>
>
> I checked this against the sh73a0 data sheet which is using 4-bit IRQ
> sense and it looks correct to me.
>
> It would nice nice if someone could test this on r8a7778 or r8a7779
> which I believe use 2-bit IRQ sense.
I've tested it on Lager. This is what prompted me to write the patch.
> Also, in the future, since the INTC hardware is kind of diverse,
> please consider including SoC information in the commit message.
OK I will.
> Acked-by: Magnus Damm <damm@opensource.se>
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2013-11-12 13:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-09 12:18 [PATCH] irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation Laurent Pinchart
2013-11-12 5:08 ` Simon Horman
2013-11-12 5:44 ` Magnus Damm
2013-11-12 13:22 ` Laurent Pinchart [this message]
2013-11-12 13:24 ` Laurent Pinchart
2013-11-13 0:54 ` Simon Horman
2013-11-13 4:14 ` Magnus Damm
2013-11-13 5:32 ` Magnus Damm
2013-11-13 6:22 ` Simon Horman
2013-11-13 11:29 ` Laurent Pinchart
2013-11-14 5:35 ` Simon Horman
2013-11-14 13:21 ` Laurent Pinchart
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