From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with archive (Exim 4.43) id 1DVm0C-0006C9-JL for mharc-grub-devel@gnu.org; Wed, 11 May 2005 03:51:33 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1DVlzy-00062d-0w for grub-devel@gnu.org; Wed, 11 May 2005 03:51:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1DVlzp-0005ys-L4 for grub-devel@gnu.org; Wed, 11 May 2005 03:51:10 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1DVlzo-0005wV-8w for grub-devel@gnu.org; Wed, 11 May 2005 03:51:09 -0400 Received: from [64.233.184.198] (helo=wproxy.gmail.com) by monty-python.gnu.org with esmtp (Exim 4.34) id 1DVm37-0002vG-53 for grub-devel@gnu.org; Wed, 11 May 2005 03:54:33 -0400 Received: by wproxy.gmail.com with SMTP id 36so63575wra for ; Wed, 11 May 2005 00:47:58 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:reply-to:to:subject:in-reply-to:mime-version:content-type:content-transfer-encoding:content-disposition:references; b=qsgspebKiTmjmVePw43bExefaJqm9B/Md6dLe2dpQ3hlZGDwgM9oJSiSfuz3I361jkowpUgZ9ShRvVNxEaIm6tSru/EQQrwliyhpxyCuRExOpio7O5ltTOZK4nJmEJr7ULFAMnqsowXJD8ysEQjTRyi7XQ2NTq1jzL5lR0f82AQ= Received: by 10.54.160.8 with SMTP id i8mr123074wre; Wed, 11 May 2005 00:47:58 -0700 (PDT) Received: by 10.54.34.79 with HTTP; Wed, 11 May 2005 00:47:58 -0700 (PDT) Message-ID: <29f91651050511004745b261aa@mail.gmail.com> Date: Wed, 11 May 2005 03:47:58 -0400 From: alfred hitch To: The development of GRUB 2 In-Reply-To: <20050511043914.GA29115@pell.home.ka8zrt.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline References: <20050510085058.DEF762FAC4@smtp.263.net> <87y8an4emu.fsf@student.han.nl> <29f91651050510032358cc2370@mail.gmail.com> <20050510121347.GA13949@openbios.org> <29f916510505101911649ac1b7@mail.gmail.com> <20050511043914.GA29115@pell.home.ka8zrt.com> Subject: Re: Fwd: memory probing X-BeenThere: grub-devel@gnu.org X-Mailman-Version: 2.1.5 Precedence: list Reply-To: The development of GRUB 2 List-Id: The development of GRUB 2 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 May 2005 07:51:23 -0000 Hi Doug, thanks a lot for your explanation, it explains quite well now to me the x86 arch. Ok coming back to the discussion, sau bios reads this info from north bridge, north bridge gets this across reboots from memory module using i2c. so, basically the info is coming from the memory chip ? We are using micron chips /banks and I just checked their data sheet, I dont see any such register there .. I see only memory init sequences etc ..=20 In IXP data sheet memory controller section mentions only one register saying size and that is being overwritten by value from bootloader (hard coded compile time #define) 2 other registes are to talk to / initiate state machine of dram init seq, etc .. Seem to me a dead wall ahead -;) Alfred So, I am feeling now that this plattform On 5/11/05, Douglas Wade Needham wrote: > First the northbridge/southbridge. Here is a pic.. >=20 > +--------+ +----------+ > | CPU |--| L2 CACHE | > +--------+ +----------+ > | > | CPU Bus > | > +-------------+ +-----+ > | Northbridge |----| RAM | > +-------------+ +-----+ > | > | Local Bus (typ. PCI) > | > +-------------+ > | Southbridge | > +-------------+ > | > | > | Periph Bus (PCI, ISA.) > | >=20 > The northbridge is primarily responsible for memory control, as well > as providing a common bus for other controllers and bridge chips. > Most of the time, this is a PCI bus. The southbridge, OTOH is the one > which is more versatile, typically acting as a bridge between the > intermediate bus and other busses used for peripherals (ISA, PCI, > etc.). Since fewer chips is often a major design goal, the > southbridge also tends to include things like an IDE controller, > floppy controller, COM ports, etc. In some cases, the north and south > bridges may be combined into a single chip. In other cases (such as > on the MCP-750), the northbridge is actually split in two, and the > local bus functionallity is separated from the memory controller > function, and both talk directly to the CPU. >=20 > As for details on your bridge chips, you will probably need to do a > NDA with some vendor to get the spec sheets which tell you the > details. The chip which has responsibility for the memory, which is > generally your northbridge (such as a Intel 440BX), will during > initialization do reads of special info on your memory modules using > I2C cycles. As a result, this chip can determine parameters such as > RAM speed, size, etc. Some bridge chips will do this as a result of a > reset, while others may require a command to be issued to do this. > Now from what I have seen, more will do it automatically when the reset > signal is asserted, instead of requiring for a command to be issued. >=20 > BTW...reading this sort of information is generally done by the boot > firmware (e.g. "BIOS"), as it is often needed so that it knows where > the bootstrap can be loaded. It is also sometimes the case that the > bootstrap will not read this information itself, but will instead > either be passed the info, or will load the main program (kernel, > etc.) based upon a set of assumptions. >=20 > - Doug >=20 > Quoting alfred hitch (alfred.hitch@gmail.com): > > Hi Stefan, > > > > thanks for your reply, > > but I am still not very clear on how this is done by say bios on x86 > > plattforms, ? > > can u please expain in more detail abt this north bridge , south > > bridge thing .. ? > > > > I would like to try and recreate the same way of probing for our set > > up, may be its not that portable , but atleast works on our series of > > products .. > > > > What registers are these ? > > > > Cheers, > > Alfred > > > > On 5/10/05, Stefan Reinauer wrote: > > > * alfred hitch [050510 12:23]: > > > > anyways, how can u get this from processor also ? > > > > > > The processor has little to nothing to do with this.. it's dependent = on > > > the northbridge and southbridge. > > > > > > > I vaguely remember see'ing some code where someone on a i386 based > > > > plattform but WITHOUT bios, used smbus protocol to talk to a device > > > > across PIIX4 to get the info. > > > > > > Which might work on one motherboard and fail on another. Even if they > > > both have a PIIX4. > > > > > > > I am not familiar with PC architecture, so can someone tell me if > > > > there is some standard chip (memory controller? ?) where one can r= ead > > > > this on PC type arch. atleast ? > > > > > > No. Not in a portable way. That's why BIOS provides the e820 table. > > > > > > > I am on a IXDP425 plattform, and so far I cannot see any such > > > > register on the data sheets .. > > > > > > They are usually not disclosed in publically available datasheets. > > > > > > Stefan > > > > > > > > > _______________________________________________ > > > Grub-devel mailing list > > > Grub-devel@gnu.org > > > http://lists.gnu.org/mailman/listinfo/grub-devel > > > > > > > > > _______________________________________________ > > Grub-devel mailing list > > Grub-devel@gnu.org > > http://lists.gnu.org/mailman/listinfo/grub-devel >=20 > -- > Douglas Wade Needham - KA8ZRT UN*X Consultant & UW/BSD kernel prog= rammer > Email: cinnion @ ka8zrt . com http://cinnion.ka8zrt.com > Disclaimer: My opinions are my own. Since I don't want them, why > should my employer, or anybody else for that matter! >=20 >=20 > _______________________________________________ > Grub-devel mailing list > Grub-devel@gnu.org > http://lists.gnu.org/mailman/listinfo/grub-devel >