From: "Chee, Tien Fong" <tien.fong.chee@altera.com>
To: Chen Huei Lok <chen.huei.lok@altera.com>, u-boot@lists.denx.de
Cc: Tom Rini <trini@konsulko.com>, Marek Vasut <marex@denx.de>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>,
Boon Khai Ng <boon.khai.ng@altera.com>,
Kok Kiang Hea <kok.kiang.hea@altera.com>
Subject: Re: [PATCH v4 12/15] ddr: altera: n5x: rename is_ddr_init_skipped() and quieten reset log
Date: Wed, 21 Oct 2026 10:27:07 +0800 [thread overview]
Message-ID: <2b13e935-9ea0-4e3f-9aa6-850e2d35b5d6@altera.com> (raw)
In-Reply-To: <20261016044047.21496-13-chen.huei.lok@altera.com>
On 16/10/2026 12:40 pm, Chen Huei Lok wrote:
> Rename is_ddr_init_skipped() to is_ddr_init() and invert its return value
> so the helper reads naturally at the call site (true means DDR must be
> initialised). The decision is otherwise unchanged: init is required on
> POR, skipped on a warm reset, and skipped on a cold reset only when the
> retention bit is set.
>
> Switch the reset-type reporting from printf() to debug() so the reset
> cause is not printed on every boot, and add the NCONFIG, JTAG_CONFIG and
> RSU_RECONFIG cases. Define reset_type_debug_print() above its first caller
> so the new call site does not trigger an implicit-declaration warning.
>
> Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com>
> ---
> drivers/ddr/altera/sdram_n5x.c | 56 +++++++++++++---------------------
> 1 file changed, 22 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
> index 244bf8ccb8c..be512cd33b1 100644
> --- a/drivers/ddr/altera/sdram_n5x.c
> +++ b/drivers/ddr/altera/sdram_n5x.c
> @@ -468,17 +468,17 @@ static enum reset_type get_reset_type(u32 reg)
> ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT;
> }
>
> -void reset_type_print(enum reset_type reset_t)
> +void reset_type_debug_print(u32 boot_scratch_cold0_reg)
> {
> - switch (reset_t) {
> + switch (get_reset_type(boot_scratch_cold0_reg)) {
> case POR_RESET:
> - printf("%s: POR is triggered\n", __func__);
> + debug("%s: POR is triggered\n", __func__);
> break;
> case WARM_RESET:
> - printf("%s: Warm reset is triggered\n", __func__);
> + debug("%s: Warm reset is triggered\n", __func__);
> break;
> case COLD_RESET:
> - printf("%s: Cold reset is triggered\n", __func__);
> + debug("%s: Cold reset is triggered\n", __func__);
> break;
> case NCONFIG:
> printf("%s: NCONFIG is triggered\n", __func__);
> @@ -490,34 +490,39 @@ void reset_type_print(enum reset_type reset_t)
> printf("%s: RSU_RECONFIG is triggered\n", __func__);
> break;
> default:
> - printf("%s: Invalid reset type\n", __func__);
> + debug("%s: Invalid reset type\n", __func__);
> }
> }
>
> -bool is_ddr_init_skipped(u32 reg, bool is_ddr_hang_be4_rst)
> +bool is_ddr_init(bool is_ddr_hang_be4_rst)
> {
> - enum reset_type reset_t = get_reset_type(reg);
> + u32 reg = readl(socfpga_get_sysmgr_addr() +
> + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
>
> - reset_type_print(reset_t);
> + reset_type_debug_print(reg);
>
> if (!is_ddr_dbe_triggered() && !is_ddr_hang_be4_rst) {
> - if (reset_t == WARM_RESET) {
> - debug("%s: DDR init is skipped\n", __func__);
> + if (get_reset_type(reg) == POR_RESET) {
> + debug("%s: DDR init is required\n", __func__);
> return true;
> }
>
> - if (reset_t == COLD_RESET) {
> + if (get_reset_type(reg) == WARM_RESET) {
> + debug("%s: DDR init is skipped\n", __func__);
> + return false;
> + }
> +
> + if (get_reset_type(reg) == COLD_RESET) {
> if (is_ddr_retention_enabled(reg)) {
> - debug("%s: DDR retention bit is set\n",
> - __func__);
> + debug("%s: DDR retention bit is set\n", __func__);
> debug("%s: DDR init is skipped\n", __func__);
> - return true;
> + return false;
> }
> }
> }
>
> debug("%s: DDR init is required\n", __func__);
> - return false;
> + return true;
> }
>
> bool is_ddr_calibration_skipped(u32 reg, bool is_ddr_hang_be4_rst)
> @@ -2811,23 +2816,6 @@ static int ddr_post_config(struct ddr_handoff *handoff, bool *need_calibrate)
> return ret;
> }
>
> -void reset_type_debug_print(u32 boot_scratch_cold0_reg)
> -{
> - switch (get_reset_type(boot_scratch_cold0_reg)) {
> - case POR_RESET:
> - debug("%s: POR is triggered\n", __func__);
> - break;
> - case WARM_RESET:
> - debug("%s: Warm reset is triggered\n", __func__);
> - break;
> - case COLD_RESET:
> - debug("%s: Cold reset is triggered\n", __func__);
> - break;
> - default:
> - debug("%s: Invalid reset type\n", __func__);
> - }
> -}
> -
> int sdram_mmr_init_full(struct udevice *dev)
> {
> u32 user_backup[2], user_backup_2nd[2];
> @@ -2860,7 +2848,7 @@ int sdram_mmr_init_full(struct udevice *dev)
> */
> writel(SOC64_CRAM_PHY_BACKUP_SKIP_MAGIC, SOC64_OCRAM_PHY_BACKUP_BASE);
>
> - if (!is_ddr_init_skipped(reg, is_ddr_hang_be4_rst)) {
> + if (is_ddr_init(is_ddr_hang_be4_rst)) {
> printf("SDRAM init in progress ...\n");
> ddr_init_inprogress(true);
>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Best regards,
Tien Fong
next prev parent reply other threads:[~2026-10-21 2:27 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20261016044047.21496-1-chen.huei.lok@altera.com>
[not found] ` <20261016044047.21496-2-chen.huei.lok@altera.com>
2026-10-21 1:55 ` [PATCH v4 01/15] misc: fs_loader: Add QSPI RAW offset loading support Chee, Tien Fong
[not found] ` <20261016044047.21496-3-chen.huei.lok@altera.com>
2026-10-21 2:07 ` [PATCH v4 02/15] arm: dts: socfpga: n5x: add DDR retention calibration backup nodes Chee, Tien Fong
[not found] ` <20261016044047.21496-4-chen.huei.lok@altera.com>
2026-10-21 2:09 ` [PATCH v4 03/15] arm: socfpga: n5x: enable QSPI mailbox before DDR init Chee, Tien Fong
[not found] ` <20261016044047.21496-5-chen.huei.lok@altera.com>
2026-10-21 2:14 ` [PATCH v4 04/15] ddr: altera: n5x: Add self-refresh support in DDR4 Chee, Tien Fong
[not found] ` <20261016044047.21496-6-chen.huei.lok@altera.com>
2026-10-21 2:16 ` [PATCH v4 05/15] configs: socfpga: n5x: enable required configs for DDR retention Chee, Tien Fong
[not found] ` <20261016044047.21496-7-chen.huei.lok@altera.com>
2026-10-21 2:18 ` [PATCH v4 06/15] ddr: altera: n5x: set DDR init progress bit for watchdog recovery Chee, Tien Fong
[not found] ` <20261016044047.21496-8-chen.huei.lok@altera.com>
2026-10-21 2:20 ` [PATCH v4 07/15] ddr: altera: n5x: re-init DDR when double-bit ECC error is detected Chee, Tien Fong
[not found] ` <20261016044047.21496-9-chen.huei.lok@altera.com>
2026-10-21 2:21 ` [PATCH v4 08/15] ddr: altera: n5x: re-init DDR after watchdog reset from init hang Chee, Tien Fong
[not found] ` <20261016044047.21496-10-chen.huei.lok@altera.com>
2026-10-21 2:22 ` [PATCH v4 09/15] ddr: altera: n5x: return error on invalid DDR controller type Chee, Tien Fong
[not found] ` <20261016044047.21496-11-chen.huei.lok@altera.com>
2026-10-21 2:24 ` [PATCH v4 10/15] ddr: altera: n5x: use correct cast for reset status register read Chee, Tien Fong
[not found] ` <20261016044047.21496-12-chen.huei.lok@altera.com>
2026-10-21 2:25 ` [PATCH v4 11/15] ddr: altera: n5x: fix debug log typo Chee, Tien Fong
[not found] ` <20261016044047.21496-13-chen.huei.lok@altera.com>
2026-10-21 2:27 ` Chee, Tien Fong [this message]
[not found] ` <20261016044047.21496-14-chen.huei.lok@altera.com>
2026-10-21 2:29 ` [PATCH v4 13/15] ddr: altera: n5x: drop always-false unsigned less-than-zero checks Chee, Tien Fong
[not found] ` <20261016044047.21496-15-chen.huei.lok@altera.com>
2026-10-21 2:30 ` [PATCH v4 14/15] ddr: altera: n5x: reconfigure DDR when mem-clk handoff changes Chee, Tien Fong
[not found] ` <20261016044047.21496-16-chen.huei.lok@altera.com>
2026-10-21 2:31 ` [PATCH v4 15/15] ddr: altera: n5x: Replay PIE handoff on DDR retention restore Chee, Tien Fong
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