From: Krzysztof Kozlowski <krzk@kernel.org>
To: Laura Nao <laura.nao@collabora.com>,
mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de,
richardcochran@gmail.com
Cc: guangjie.song@mediatek.com, wenst@chromium.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
kernel@collabora.com
Subject: Re: [PATCH 29/30] dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding
Date: Mon, 23 Jun 2025 14:13:35 +0200 [thread overview]
Message-ID: <2bc23bcf-0021-44dd-ae42-9ef0e95e3b32@kernel.org> (raw)
In-Reply-To: <20250623102940.214269-30-laura.nao@collabora.com>
On 23/06/2025 12:29, Laura Nao wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> Add a binding for the PEXTP0/1 and UFS reset controllers found in
> the MediaTek MT8196 Chromebook SoC.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Laura Nao <laura.nao@collabora.com>
> ---
> .../reset/mediatek,mt8196-resets.h | 26 +++++++++++++++++++
This belongs to the binding doc.
> 1 file changed, 26 insertions(+)
> create mode 100644 include/dt-bindings/reset/mediatek,mt8196-resets.h
>
> diff --git a/include/dt-bindings/reset/mediatek,mt8196-resets.h b/include/dt-bindings/reset/mediatek,mt8196-resets.h
> new file mode 100644
> index 000000000000..1a01b2b01f7f
> --- /dev/null
> +++ b/include/dt-bindings/reset/mediatek,mt8196-resets.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */
Wrong license, use standard ones.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-06-23 15:36 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-23 10:29 [PATCH 00/30] Add support for MT8196 clock controllers Laura Nao
2025-06-23 10:29 ` [PATCH 01/30] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-06-23 10:29 ` [PATCH 02/30] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-06-23 10:29 ` [PATCH 03/30] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-06-23 10:29 ` [PATCH 04/30] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-06-23 10:29 ` [PATCH 05/30] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-06-23 10:29 ` [PATCH 06/30] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-06-23 10:29 ` [PATCH 07/30] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-06-23 10:29 ` [PATCH 08/30] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-06-23 10:29 ` [PATCH 09/30] dt-bindings: clock: mediatek: Describe MT8196 peripheral clock controllers Laura Nao
2025-06-23 12:12 ` Krzysztof Kozlowski
2025-06-23 12:28 ` AngeloGioacchino Del Regno
2025-06-23 10:29 ` [PATCH 10/30] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-06-23 10:29 ` [PATCH 11/30] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-06-23 10:29 ` [PATCH 12/30] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-06-23 10:29 ` [PATCH 13/30] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-06-23 10:29 ` [PATCH 14/30] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-06-23 10:29 ` [PATCH 15/30] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-06-23 10:29 ` [PATCH 16/30] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-06-23 10:29 ` [PATCH 17/30] clk: mediatek: Add MT8196 adsp " Laura Nao
2025-06-23 10:29 ` [PATCH 18/30] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-06-23 10:29 ` [PATCH 19/30] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-06-23 10:29 ` [PATCH 20/30] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-06-23 10:29 ` [PATCH 21/30] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-06-23 10:29 ` [PATCH 22/30] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-06-23 10:29 ` [PATCH 23/30] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-06-23 10:29 ` [PATCH 24/30] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-06-24 6:40 ` kernel test robot
2025-06-23 10:29 ` [PATCH 25/30] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-06-23 10:29 ` [PATCH 26/30] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-06-23 10:29 ` [PATCH 27/30] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-06-23 10:29 ` [PATCH 28/30] clk: mediatek: Add MT8196 vencsys " Laura Nao
2025-06-23 10:29 ` [PATCH 29/30] dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding Laura Nao
2025-06-23 12:13 ` Krzysztof Kozlowski [this message]
2025-06-23 12:22 ` AngeloGioacchino Del Regno
2025-06-23 10:29 ` [PATCH 30/30] clk: mediatek: mt8196: Add UFS and PEXTP0/1 reset controllers Laura Nao
2025-06-23 12:14 ` Krzysztof Kozlowski
2025-06-23 12:33 ` AngeloGioacchino Del Regno
2025-06-23 11:34 ` [PATCH 00/30] Add support for MT8196 clock controllers AngeloGioacchino Del Regno
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2bc23bcf-0021-44dd-ae42-9ef0e95e3b32@kernel.org \
--to=krzk@kernel.org \
--cc=angelogioacchino.delregno@collabora.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=guangjie.song@mediatek.com \
--cc=kernel@collabora.com \
--cc=krzk+dt@kernel.org \
--cc=laura.nao@collabora.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=mturquette@baylibre.com \
--cc=netdev@vger.kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=richardcochran@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=wenst@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.