From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71E0FC47422 for ; Mon, 29 Jan 2024 11:33:01 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CB1B987A00; Mon, 29 Jan 2024 12:32:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="QX8mQJJ4"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 977DE87CAD; Mon, 29 Jan 2024 12:32:58 +0100 (CET) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 81E9F87956 for ; Mon, 29 Jan 2024 12:32:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=a-nandan@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40TBWeqK062274; Mon, 29 Jan 2024 05:32:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706527960; bh=xDICBN/iTyEf23Gl8/LlclqLYcYNutuY85jMIshgd10=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=QX8mQJJ4lIXN9dlbQ64NxezpxIb2vFwxE2uAGGIkbDRC6wd05SU0CvjcuUvB9EYiI sRJp/pEBxPnpO7turS4VYgXQQPt4tndj0ADq2k9lN5E4Uqh6xSY1d5jaw+T26+UAAj YJVjyUbhCeTfhJ9wTnQ+NTm0GTky0p5GhkwCPlkI= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40TBWeTT050163 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 Jan 2024 05:32:40 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 Jan 2024 05:32:40 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 Jan 2024 05:32:40 -0600 Received: from [10.24.68.115] (ti.dhcp.ti.com [10.24.68.115] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TBWXag020172; Mon, 29 Jan 2024 05:32:34 -0600 Message-ID: <2d566dde-5428-400e-a30e-47cb80ccf5d1@ti.com> Date: Mon, 29 Jan 2024 17:02:32 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 02/16] arm: mach-k3: Add basic support for J784S4 SoC definition To: Nishanth Menon CC: Hari Nagalla , Lukasz Majewski , Sean Anderson , Jaehoon Chung , Neha Malcom Francis , Simon Glass , Andrew Davis , Kamlesh Gurudasani , Dasnavis Sabiya , Manorit Chawdhry , Aradhya Bhatia , Bryan Brattlof , Christian Gmeiner , Heinrich Schuchardt , Marcel Ziswiler , Roger Quadros , Jayesh Choudhary , Ralph Siemsen , Marek Vasut , Rasmus Villemoes , , Sinthu Raja M , Udit Kumar References: <20240119175043.3904751-1-a-nandan@ti.com> <20240119175043.3904751-3-a-nandan@ti.com> <20240119193403.kgzt2zcxa55wexr3@skedaddle> <20240123204710.hlv4x4y3gst7utoe@squealing> Content-Language: en-US From: Apurva Nandan In-Reply-To: <20240123204710.hlv4x4y3gst7utoe@squealing> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Hi, On 24/01/24 02:17, Nishanth Menon wrote: > On 20:21-20240123, Apurva Nandan wrote: > [...] >>>> +void k3_mem_init(void) >>>> +{ >>>> + struct udevice *dev; >>>> + int ret, ctr = 1; >>>> + >>>> + if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) { >>>> + ret = uclass_get_device(UCLASS_RAM, 0, &dev); >>>> + if (ret) >>>> + panic("DRAM 0 init failed: %d\n", ret); >>>> + >>>> + while (dev) { >>> why loop on dev? is it possible to have ret != 0 and dev = 0? >>> >> Some variable needs to be used for loop condition, do you want it to be ret? >> or maybe you can suggest your idea for this please. >>>> + ret = uclass_next_device_err(&dev); >>>> + if (ret) { >>>> + printf("Initialized %d DRAM controllers\n", ctr); >>>> + break; >>>> + } >>>> + ctr++; >>> What is the use of ctr++ ?? please do a limit check for instances. >> This is to keep the logic independent of board evm, so that no include of >> EVM config is needed. >> ctr is just used to notify user about how many DDR are up during boot, else >> it is not needed. >> >> I can remove the ctr and printf, if you want. >> >> For a limit check, how can we get number of DDR instances on the EVM, I >> don't know, can you please suggest some way? >> >> There is no config that stores this info afaik. > Why? J784s4 has only specific number of controllerns, correct? > > A variant of the below -> but still have a question: > > while (ctrl < J784S4_MAX_CONTROLLERS) { Is J784S4_MAX_CONTROLLERS going to be a #define in j784s4_init.c Or a Kconfig option like: config DDR_MAX_CONTROLLERS     int "Max number of DRAM controllers"     default 4 if SOC_K3_J784S4     default 1     help > ret = uclass_next_device_err(&ret); > if (ret) /* Question: How do we differentiate between valid > * failure and next instance not being present? */ > break; how about:             ...             if (ret == -ENODEV)                 break;             if (ret)                  panic("DRAM %d init failed: %d\n", ctrl,  ret);             ... > ctrl++; > } > > info("Initialized %d DRAM controllers\n", ctrl - 1); >>> [...] >>> >>> Next time, please respond to the review comment questions so that I >>> know that you have considered and decided something is not necessary >>> or something was missed in the new version - for example what happened >>> to mmc_stop/restart? >> mmc_stop/restart were removed (mentioned in series changelog) > Mentioning in diffstat of the patch helps give people the context of the > change w.r.t the path itself. okay -- Regards, Apurva Nandan, Texas Instruments.