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[2003:ca:b741:f1d0:3123:f9e9:b484:6874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc263f0sm81274495e9.9.2025.01.30.23.13.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Jan 2025 23:13:39 -0800 (PST) Message-ID: <2d5b51e9-db32-4e46-97c8-2644081b7e33@suse.com> Date: Fri, 31 Jan 2025 08:13:37 +0100 Precedence: bulk X-Mailing-List: regressions@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Config space access to Mediatek MT7922 doesn't work after device reset in Xen PV dom0 (regression, Linux 6.12) To: Bjorn Helgaas Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Bjorn Helgaas , =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Boris Ostrovsky , xen-devel , linux-kernel@vger.kernel.org, regressions@lists.linux.dev, Felix Fietkau , Lorenzo Bianconi , Ryder Lee References: <20250130213123.GA633869@bhelgaas> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250130213123.GA633869@bhelgaas> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 30.01.2025 22:31, Bjorn Helgaas wrote: > On Thu, Jan 30, 2025 at 10:30:33AM +0100, Jan Beulich wrote: >> On 30.01.2025 05:55, Marek Marczykowski-Górecki wrote: >>> (XEN) d0v1 conf read cf8 0x80010088 bytes 2 offset 2 data 0x9 > > PCIe Cap at 0x80, PCI_EXP_DEVCTL is 0x08, PCI_EXP_DEVSTA is 0x0a. > > 0x80010088 would be PCI_EXP_DEVCTL (a 2-byte register), maybe offset 2 > gets us to PCI_EXP_DEVSTA? Not sure. > > 0x0001 PCI_EXP_DEVSTA_CED /* Correctable Error Detected */ > 0x0008 PCI_EXP_DEVSTA_URD /* Unsupported Request Detected */ > > Not impossible that these would be set. Lots of URs happen during > enumeration and we're not very good about cleaning these up. > Correctable errors are common for some devices. lspci -vv would > decode the PCIe cap registers, including this. > >>> (XEN) d0v1 conf read cf8 0x80010088 bytes 2 offset 0 data 0x2910 > > PCI_EXP_DEVCTL: > 0x2000 PCI_EXP_DEVCTL_READRQ_512B > 0x0800 PCI_EXP_DEVCTL_NOSNOOP_EN > 0x0100 PCI_EXP_DEVCTL_EXT_TAG > 0x0010 PCI_EXP_DEVCTL_RELAX_EN > >>> (XEN) d0v1 conf write cf8 0x80010088 bytes 2 offset 0 data 0xa910 > > PCI_EXP_DEVCTL: > set 0x8000 PCI_EXP_DEVCTL_BCR_FLR > > This looks like the actual FLR being initiated. > >> This is the express capability's Link Control 2 Register afaict. > > Unless I'm missing something this is actually Device Control. So far > I think this all looks OK. The next part: What you say is very plausible as far as the observed behavior goes, but: According to the lspci output provided earlier the express capability is at 58 (hex). Hence here we're 30 (hex) into the capability, which according to the spec I'm looking at is Link Control 2. Yet as said - with what you say being plausible, likely I'm simply getting something very wrong. Jan