[PATCH v3 04/12] rockchip: clk: rk3288: add SCLK_OTGPHYx enable and disable

[Johan Jonker <jbx6244@gmail.com>]

Add rk3288 SCLK_OTGPHYx enable and disable.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(13), 4, GFLAGS),
	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(13), 5, GFLAGS),
	GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(13), 6, GFLAGS),
---
 drivers/clk/rockchip/clk_rk3288.c | 40 +++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index a4ff1c41abb8..07d539a9f703 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -946,7 +946,47 @@ static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *par
 	return -ENOENT;
 }

+static int rk3288_clk_enable(struct clk *clk)
+{
+	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case SCLK_OTGPHY0:
+		rk_clrreg(&priv->cru->cru_clkgate_con[13], BIT(4));
+		break;
+	case SCLK_OTGPHY1:
+		rk_clrreg(&priv->cru->cru_clkgate_con[13], BIT(5));
+		break;
+	case SCLK_OTGPHY2:
+		rk_clrreg(&priv->cru->cru_clkgate_con[13], BIT(6));
+		break;
+	}
+
+	return 0;
+}
+
+static int rk3288_clk_disable(struct clk *clk)
+{
+	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case SCLK_OTGPHY0:
+		rk_setreg(&priv->cru->cru_clkgate_con[13], BIT(4));
+		break;
+	case SCLK_OTGPHY1:
+		rk_setreg(&priv->cru->cru_clkgate_con[13], BIT(5));
+		break;
+	case SCLK_OTGPHY2:
+		rk_setreg(&priv->cru->cru_clkgate_con[13], BIT(6));
+		break;
+	}
+
+	return 0;
+}
+
 static struct clk_ops rk3288_clk_ops = {
+	.disable	= rk3288_clk_disable,
+	.enable		= rk3288_clk_enable,
 	.get_rate	= rk3288_clk_get_rate,
 	.set_rate	= rk3288_clk_set_rate,
 #if CONFIG_IS_ENABLED(OF_REAL)
--
2.39.5