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Thu, 19 Oct 2023 00:59:37 GMT Received: from [10.71.110.254] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 18 Oct 2023 17:59:37 -0700 Message-ID: <2dace097-affe-4bc6-ac7c-b5606bd86a89@quicinc.com> Date: Wed, 18 Oct 2023 17:59:22 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v6 08/10] drm/msm/dpu: Allow NULL FBs in atomic commit Content-Language: en-US To: Dmitry Baryshkov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Clark , Sean Paul , Marijn Suijten CC: , , , , , , , , , , References: <20230828-solid-fill-v6-0-a820efcce852@quicinc.com> <20230828-solid-fill-v6-8-a820efcce852@quicinc.com> <494ede51-46bf-437b-98b8-2460f4c40285@linaro.org> From: Jessica Zhang In-Reply-To: <494ede51-46bf-437b-98b8-2460f4c40285@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: nV9ckG_qzcqOWifFAWc49DtNzwNouqat X-Proofpoint-GUID: nV9ckG_qzcqOWifFAWc49DtNzwNouqat X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-19_01,2023-10-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310190005 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 9/24/2023 3:29 AM, Dmitry Baryshkov wrote: > On 29/08/2023 03:05, Jessica Zhang wrote: >> Since solid fill planes allow for a NULL framebuffer in a valid commit, >> add NULL framebuffer checks to atomic commit calls within DPU. >> >> Reviewed-by: Dmitry Baryshkov >> Signed-off-by: Jessica Zhang >> --- >>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  |  9 ++++++- >>   drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 41 >> ++++++++++++++++++++----------- >>   2 files changed, 34 insertions(+), 16 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> index 8ce7586e2ddf..5e845510e8c1 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> @@ -451,6 +451,7 @@ static void _dpu_crtc_blend_setup_mixer(struct >> drm_crtc *crtc, >>       struct drm_plane_state *state; >>       struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); >>       struct dpu_plane_state *pstate = NULL; >> +    const struct msm_format *fmt; >>       struct dpu_format *format; >>       struct dpu_hw_ctl *ctl = mixer->lm_ctl; >> @@ -470,7 +471,13 @@ static void _dpu_crtc_blend_setup_mixer(struct >> drm_crtc *crtc, >>           pstate = to_dpu_plane_state(state); >>           fb = state->fb; >> -        format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); >> +        if (drm_plane_solid_fill_enabled(state)) >> +            fmt = dpu_get_msm_format(&_dpu_crtc_get_kms(crtc)->base, >> +                    DRM_FORMAT_ABGR8888, 0); >> +        else >> +            fmt = msm_framebuffer_format(pstate->base.fb); >> + >> +        format = to_dpu_format(fmt); >>           if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) >>               bg_alpha_enable = true; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c >> index c2aaaded07ed..114c803ff99b 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c >> @@ -837,8 +837,13 @@ static int dpu_plane_atomic_check(struct >> drm_plane *plane, >>       pipe_cfg->dst_rect = new_plane_state->dst; >> -    fb_rect.x2 = new_plane_state->fb->width; >> -    fb_rect.y2 = new_plane_state->fb->height; >> +    if (drm_plane_solid_fill_enabled(new_plane_state)) >> +        return 0; > > This would skip all the width checks, dpu_plane_atomic_check_pipe(), > etc. Could you please confirm that all of those checks are irrelevant > for solid fill? Hi Dmitry, Good point -- I think it would be good to keep the rect and pipe checks for solid fill. > >> + >> +    if (new_plane_state->pixel_source == DRM_PLANE_PIXEL_SOURCE_FB && >> new_plane_state->fb) { >> +        fb_rect.x2 = new_plane_state->fb->width; >> +        fb_rect.y2 = new_plane_state->fb->height; >> +    } >>       /* Ensure fb size is supported */ >>       if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || >> @@ -1082,21 +1087,32 @@ static void >> dpu_plane_sspp_atomic_update(struct drm_plane *plane) >>       struct drm_crtc *crtc = state->crtc; >>       struct drm_framebuffer *fb = state->fb; >>       bool is_rt_pipe; >> -    const struct dpu_format *fmt = >> -        to_dpu_format(msm_framebuffer_format(fb)); >> +    const struct dpu_format *fmt; >>       struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; >>       struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; >>       struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); >>       struct msm_gem_address_space *aspace = kms->base.aspace; >>       struct dpu_hw_fmt_layout layout; >>       bool layout_valid = false; >> -    int ret; >> -    ret = dpu_format_populate_layout(aspace, fb, &layout); >> -    if (ret) >> -        DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); >> -    else >> -        layout_valid = true; >> +    if (state->pixel_source == DRM_PLANE_PIXEL_SOURCE_FB && fb) { >> +        int ret; >> + >> +        fmt = to_dpu_format(msm_framebuffer_format(fb)); >> + >> +        ret = dpu_format_populate_layout(aspace, fb, &layout); >> +        if (ret) >> +            DPU_ERROR_PLANE(pdpu, "failed to get format layout, >> %d\n", ret); >> +        else >> +            layout_valid = true; >> + >> +        DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " >> DRM_RECT_FMT >> +                ", %4.4s ubwc %d\n", fb->base.id, >> DRM_RECT_FP_ARG(&state->src), >> +                crtc->base.id, DRM_RECT_ARG(&state->dst), >> +                (char *)&fmt->base.pixel_format, >> DPU_FORMAT_IS_UBWC(fmt)); >> +    } else { >> +        fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); > > #define DPU_SOLID_FILL_FORMAT ? Acked. > > Also, I don't think that solid_fill planes consume bandwidth, so this > likely needs to be fixed too. You're right -- I think we can actually return early here if solid fill is enabled. Thanks, Jessica Zhang > > >> +    } >>       pstate->pending = true; >> @@ -1104,11 +1120,6 @@ static void dpu_plane_sspp_atomic_update(struct >> drm_plane *plane) >>       pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); >>       pdpu->is_rt_pipe = is_rt_pipe; >> -    DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " >> DRM_RECT_FMT >> -            ", %4.4s ubwc %d\n", fb->base.id, >> DRM_RECT_FP_ARG(&state->src), >> -            crtc->base.id, DRM_RECT_ARG(&state->dst), >> -            (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); >> - >>       dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, >>                      drm_mode_vrefresh(&crtc->mode), >>                      layout_valid ? &layout : NULL); >> > > -- > With best wishes > Dmitry > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88C8BCDB47E for ; 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Thu, 19 Oct 2023 00:59:38 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39J0xbTu000956 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Oct 2023 00:59:37 GMT Received: from [10.71.110.254] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 18 Oct 2023 17:59:37 -0700 Message-ID: <2dace097-affe-4bc6-ac7c-b5606bd86a89@quicinc.com> Date: Wed, 18 Oct 2023 17:59:22 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v6 08/10] drm/msm/dpu: Allow NULL FBs in atomic commit Content-Language: en-US To: Dmitry Baryshkov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Clark , Sean Paul , Marijn Suijten References: <20230828-solid-fill-v6-0-a820efcce852@quicinc.com> <20230828-solid-fill-v6-8-a820efcce852@quicinc.com> <494ede51-46bf-437b-98b8-2460f4c40285@linaro.org> From: Jessica Zhang In-Reply-To: <494ede51-46bf-437b-98b8-2460f4c40285@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: nV9ckG_qzcqOWifFAWc49DtNzwNouqat X-Proofpoint-GUID: nV9ckG_qzcqOWifFAWc49DtNzwNouqat X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-19_01,2023-10-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310190005 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sebastian.wick@redhat.com, quic_abhinavk@quicinc.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, ppaalanen@gmail.com, laurent.pinchart@ideasonboard.com, linux-arm-msm@vger.kernel.org, wayland-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 9/24/2023 3:29 AM, Dmitry Baryshkov wrote: > On 29/08/2023 03:05, Jessica Zhang wrote: >> Since solid fill planes allow for a NULL framebuffer in a valid commit, >> add NULL framebuffer checks to atomic commit calls within DPU. >> >> Reviewed-by: Dmitry Baryshkov >> Signed-off-by: Jessica Zhang >> --- >>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  |  9 ++++++- >>   drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 41 >> ++++++++++++++++++++----------- >>   2 files changed, 34 insertions(+), 16 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> index 8ce7586e2ddf..5e845510e8c1 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> @@ -451,6 +451,7 @@ static void _dpu_crtc_blend_setup_mixer(struct >> drm_crtc *crtc, >>       struct drm_plane_state *state; >>       struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); >>       struct dpu_plane_state *pstate = NULL; >> +    const struct msm_format *fmt; >>       struct dpu_format *format; >>       struct dpu_hw_ctl *ctl = mixer->lm_ctl; >> @@ -470,7 +471,13 @@ static void _dpu_crtc_blend_setup_mixer(struct >> drm_crtc *crtc, >>           pstate = to_dpu_plane_state(state); >>           fb = state->fb; >> -        format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); >> +        if (drm_plane_solid_fill_enabled(state)) >> +            fmt = dpu_get_msm_format(&_dpu_crtc_get_kms(crtc)->base, >> +                    DRM_FORMAT_ABGR8888, 0); >> +        else >> +            fmt = msm_framebuffer_format(pstate->base.fb); >> + >> +        format = to_dpu_format(fmt); >>           if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) >>               bg_alpha_enable = true; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c >> index c2aaaded07ed..114c803ff99b 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c >> @@ -837,8 +837,13 @@ static int dpu_plane_atomic_check(struct >> drm_plane *plane, >>       pipe_cfg->dst_rect = new_plane_state->dst; >> -    fb_rect.x2 = new_plane_state->fb->width; >> -    fb_rect.y2 = new_plane_state->fb->height; >> +    if (drm_plane_solid_fill_enabled(new_plane_state)) >> +        return 0; > > This would skip all the width checks, dpu_plane_atomic_check_pipe(), > etc. Could you please confirm that all of those checks are irrelevant > for solid fill? Hi Dmitry, Good point -- I think it would be good to keep the rect and pipe checks for solid fill. > >> + >> +    if (new_plane_state->pixel_source == DRM_PLANE_PIXEL_SOURCE_FB && >> new_plane_state->fb) { >> +        fb_rect.x2 = new_plane_state->fb->width; >> +        fb_rect.y2 = new_plane_state->fb->height; >> +    } >>       /* Ensure fb size is supported */ >>       if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || >> @@ -1082,21 +1087,32 @@ static void >> dpu_plane_sspp_atomic_update(struct drm_plane *plane) >>       struct drm_crtc *crtc = state->crtc; >>       struct drm_framebuffer *fb = state->fb; >>       bool is_rt_pipe; >> -    const struct dpu_format *fmt = >> -        to_dpu_format(msm_framebuffer_format(fb)); >> +    const struct dpu_format *fmt; >>       struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; >>       struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; >>       struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); >>       struct msm_gem_address_space *aspace = kms->base.aspace; >>       struct dpu_hw_fmt_layout layout; >>       bool layout_valid = false; >> -    int ret; >> -    ret = dpu_format_populate_layout(aspace, fb, &layout); >> -    if (ret) >> -        DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); >> -    else >> -        layout_valid = true; >> +    if (state->pixel_source == DRM_PLANE_PIXEL_SOURCE_FB && fb) { >> +        int ret; >> + >> +        fmt = to_dpu_format(msm_framebuffer_format(fb)); >> + >> +        ret = dpu_format_populate_layout(aspace, fb, &layout); >> +        if (ret) >> +            DPU_ERROR_PLANE(pdpu, "failed to get format layout, >> %d\n", ret); >> +        else >> +            layout_valid = true; >> + >> +        DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " >> DRM_RECT_FMT >> +                ", %4.4s ubwc %d\n", fb->base.id, >> DRM_RECT_FP_ARG(&state->src), >> +                crtc->base.id, DRM_RECT_ARG(&state->dst), >> +                (char *)&fmt->base.pixel_format, >> DPU_FORMAT_IS_UBWC(fmt)); >> +    } else { >> +        fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); > > #define DPU_SOLID_FILL_FORMAT ? Acked. > > Also, I don't think that solid_fill planes consume bandwidth, so this > likely needs to be fixed too. You're right -- I think we can actually return early here if solid fill is enabled. Thanks, Jessica Zhang > > >> +    } >>       pstate->pending = true; >> @@ -1104,11 +1120,6 @@ static void dpu_plane_sspp_atomic_update(struct >> drm_plane *plane) >>       pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); >>       pdpu->is_rt_pipe = is_rt_pipe; >> -    DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " >> DRM_RECT_FMT >> -            ", %4.4s ubwc %d\n", fb->base.id, >> DRM_RECT_FP_ARG(&state->src), >> -            crtc->base.id, DRM_RECT_ARG(&state->dst), >> -            (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); >> - >>       dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, >>                      drm_mode_vrefresh(&crtc->mode), >>                      layout_valid ? &layout : NULL); >> > > -- > With best wishes > Dmitry >