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Tue, 14 May 2024 04:38:13 -0700 (PDT) Message-ID: <2dda41cc-0d43-445f-b96b-38fbb799bf45@ventanamicro.com> Date: Tue, 14 May 2024 08:38:08 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] target/riscv: Remove experimental prefix from "B" extension To: Rob Bradford , qemu-devel@nongnu.org Cc: Andrew Jones , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , "open list:RISC-V TCG CPUs" References: <20240514110217.22516-1-rbradford@rivosinc.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20240514110217.22516-1-rbradford@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 5/14/24 08:02, Rob Bradford wrote: > This extension has now been ratified: > https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be > removed. > > Since this is now a ratified extension add it to the list of extensions > included in the "max" CPU variant. > > Signed-off-by: Rob Bradford > Reviewed-by: Andrew Jones > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/cpu.c | 2 +- > target/riscv/tcg/tcg-cpu.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index eb1a2e7d6d..861d9f4350 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1396,7 +1396,7 @@ static const MISAExtInfo misa_ext_info_arr[] = { > MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), > MISA_EXT_INFO(RVV, "v", "Vector operations"), > MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), > - MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)") > + MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)") > }; > > static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 40054a391a..164a13ad0f 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -1281,7 +1281,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) > const RISCVCPUMultiExtConfig *prop; > > /* Enable RVG, RVJ and RVV that are disabled by default */ > - riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV); > + riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV); > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > isa_ext_update_enabled(cpu, prop->offset, true);