From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6880E2A9D7 for ; Thu, 18 May 2023 07:17:58 +0000 (UTC) Received: from lhrpeml100001.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4QMLmX68xMz6J7Jm; Thu, 18 May 2023 15:13:32 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (7.191.163.240) by lhrpeml100001.china.huawei.com (7.191.160.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 18 May 2023 08:17:48 +0100 Received: from lhrpeml500005.china.huawei.com ([7.191.163.240]) by lhrpeml500005.china.huawei.com ([7.191.163.240]) with mapi id 15.01.2507.023; Thu, 18 May 2023 08:17:48 +0100 From: Shameerali Kolothum Thodi To: Jing Zhang , KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton CC: Will Deacon , Paolo Bonzini , "James Morse" , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta Subject: RE: [PATCH v9 1/5] KVM: arm64: Save ID registers' sanitized value per guest Thread-Topic: [PATCH v9 1/5] KVM: arm64: Save ID registers' sanitized value per guest Thread-Index: AQHZiIZI1S6VidLz8kuuQndld0olVq9fng1A Date: Thu, 18 May 2023 07:17:48 +0000 Message-ID: <2e727b02fe9141098ed474ef49ddc495@huawei.com> References: <20230517061015.1915934-1-jingzhangos@google.com> <20230517061015.1915934-2-jingzhangos@google.com> In-Reply-To: <20230517061015.1915934-2-jingzhangos@google.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.178] Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CFilter-Loop: Reflected DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogSmluZyBaaGFuZyBbbWFp bHRvOmppbmd6aGFuZ29zQGdvb2dsZS5jb21dDQo+IFNlbnQ6IDE3IE1heSAyMDIzIDA3OjEwDQo+ IFRvOiBLVk0gPGt2bUB2Z2VyLmtlcm5lbC5vcmc+OyBLVk1BUk0gPGt2bWFybUBsaXN0cy5saW51 eC5kZXY+Ow0KPiBBUk1MaW51eCA8bGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3Jn PjsgTWFyYyBaeW5naWVyDQo+IDxtYXpAa2VybmVsLm9yZz47IE9saXZlciBVcHRvbiA8b3VwdG9u QGdvb2dsZS5jb20+DQo+IENjOiBXaWxsIERlYWNvbiA8d2lsbEBrZXJuZWwub3JnPjsgUGFvbG8g Qm9uemluaSA8cGJvbnppbmlAcmVkaGF0LmNvbT47DQo+IEphbWVzIE1vcnNlIDxqYW1lcy5tb3Jz ZUBhcm0uY29tPjsgQWxleGFuZHJ1IEVsaXNlaQ0KPiA8YWxleGFuZHJ1LmVsaXNlaUBhcm0uY29t PjsgU3V6dWtpIEsgUG91bG9zZSA8c3V6dWtpLnBvdWxvc2VAYXJtLmNvbT47DQo+IEZ1YWQgVGFi YmEgPHRhYmJhQGdvb2dsZS5jb20+OyBSZWlqaSBXYXRhbmFiZSA8cmVpaml3QGdvb2dsZS5jb20+ Ow0KPiBSYWdoYXZlbmRyYSBSYW8gQW5hbnRhIDxyYW5hbnRhQGdvb2dsZS5jb20+OyBKaW5nIFpo YW5nDQo+IDxqaW5nemhhbmdvc0Bnb29nbGUuY29tPg0KPiBTdWJqZWN0OiBbUEFUQ0ggdjkgMS81 XSBLVk06IGFybTY0OiBTYXZlIElEIHJlZ2lzdGVycycgc2FuaXRpemVkIHZhbHVlIHBlcg0KPiBn dWVzdA0KPiANCj4gSW50cm9kdWNlIGlkX3JlZ3NbXSBpbiBrdm1fYXJjaCBhcyBhIHN0b3JhZ2Ug b2YgZ3Vlc3QncyBJRCByZWdpc3RlcnMsDQo+IGFuZCBzYXZlIElEIHJlZ2lzdGVycycgc2FuaXRp emVkIHZhbHVlIGluIHRoZSBhcnJheSBhdCBLVk1fQ1JFQVRFX1ZNLg0KPiBVc2UgdGhlIHNhdmVk IG9uZXMgd2hlbiBJRCByZWdpc3RlcnMgYXJlIHJlYWQgYnkgdGhlIGd1ZXN0IG9yDQo+IHVzZXJz cGFjZSAodmlhIEtWTV9HRVRfT05FX1JFRykuDQo+IA0KPiBObyBmdW5jdGlvbmFsIGNoYW5nZSBp bnRlbmRlZC4NCj4gDQo+IENvLWRldmVsb3BlZC1ieTogUmVpamkgV2F0YW5hYmUgPHJlaWppd0Bn b29nbGUuY29tPg0KPiBTaWduZWQtb2ZmLWJ5OiBSZWlqaSBXYXRhbmFiZSA8cmVpaml3QGdvb2ds ZS5jb20+DQo+IFNpZ25lZC1vZmYtYnk6IEppbmcgWmhhbmcgPGppbmd6aGFuZ29zQGdvb2dsZS5j b20+DQo+IC0tLQ0KPiAgYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9rdm1faG9zdC5oIHwgMjAgKysr KysrKysrDQo+ICBhcmNoL2FybTY0L2t2bS9hcm0uYyAgICAgICAgICAgICAgfCAgMSArDQo+ICBh cmNoL2FybTY0L2t2bS9zeXNfcmVncy5jICAgICAgICAgfCA2OQ0KPiArKysrKysrKysrKysrKysr KysrKysrKysrLS0tLS0tDQo+ICBhcmNoL2FybTY0L2t2bS9zeXNfcmVncy5oICAgICAgICAgfCAg NyArKysrDQo+ICA0IGZpbGVzIGNoYW5nZWQsIDg1IGluc2VydGlvbnMoKyksIDEyIGRlbGV0aW9u cygtKQ0KPiANCj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20va3ZtX2hvc3Qu aA0KPiBiL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20va3ZtX2hvc3QuaA0KPiBpbmRleCA3ZTdlMTll ZjY5OTMuLjk0OWE0YTc4Mjg0NCAxMDA2NDQNCj4gLS0tIGEvYXJjaC9hcm02NC9pbmNsdWRlL2Fz bS9rdm1faG9zdC5oDQo+ICsrKyBiL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20va3ZtX2hvc3QuaA0K PiBAQCAtMTc4LDYgKzE3OCwyMSBAQCBzdHJ1Y3Qga3ZtX3NtY2NjX2ZlYXR1cmVzIHsNCj4gIAl1 bnNpZ25lZCBsb25nIHZlbmRvcl9oeXBfYm1hcDsNCj4gIH07DQo+IA0KPiArLyoNCj4gKyAqIEVt dWxhdGVkIENQVSBJRCByZWdpc3RlcnMgcGVyIFZNDQo+ICsgKiAoT3AwLCBPcDEsIENSbiwgQ1Jt LCBPcDIpIG9mIHRoZSBJRCByZWdpc3RlcnMgdG8gYmUgc2F2ZWQgaW4gaXQNCj4gKyAqIGlzICgz LCAwLCAwLCBjcm0sIG9wMiksIHdoZXJlIDE8PWNybTw4LCAwPD1vcDI8OC4NCj4gKyAqDQo+ICsg KiBUaGVzZSBlbXVsYXRlZCBpZHJlZ3MgYXJlIFZNLXdpZGUsIGJ1dCBhY2Nlc3NlZCBmcm9tIHRo ZSBjb250ZXh0IG9mIGENCj4gdkNQVS4NCj4gKyAqIEFjY2VzcyB0byBpZCByZWdzIGFyZSBndWFy ZGVkIGJ5IGt2bV9hcmNoLmNvbmZpZ19sb2NrLg0KPiArICovDQo+ICsjZGVmaW5lIEtWTV9BUk1f SURfUkVHX05VTQk1Ng0KPiArI2RlZmluZSBJRFJFR19JRFgoaWQpCQkoKChzeXNfcmVnX0NSbShp ZCkgLSAxKSA8PCAzKSB8IHN5c19yZWdfT3AyKGlkKSkNCj4gKyNkZWZpbmUgSURSRUcoa3ZtLCBp ZCkJCSgoa3ZtKS0+YXJjaC5pZHJlZ3MucmVnc1tJRFJFR19JRFgoaWQpXSkNCj4gK3N0cnVjdCBr dm1faWRyZWdzIHsNCj4gKwl1NjQgcmVnc1tLVk1fQVJNX0lEX1JFR19OVU1dOw0KPiArfTsNCj4g DQoNCk5vdCBzdXJlIHdlIHJlYWxseSBuZWVkIHRoaXMgc3RydWN0IGhlcmUuIFdoeSBjYW4ndCB0 aGlzIGFycmF5IGJlIG1vdmVkIHRvDQpzdHJ1Y3Qga3ZtX2FyY2ggZGlyZWN0bHk/DQoNCj4gIHR5 cGVkZWYgdW5zaWduZWQgaW50IHBrdm1faGFuZGxlX3Q7DQo+IA0KPiAgc3RydWN0IGt2bV9wcm90 ZWN0ZWRfdm0gew0KPiBAQCAtMjUzLDYgKzI2OCw5IEBAIHN0cnVjdCBrdm1fYXJjaCB7DQo+ICAJ c3RydWN0IGt2bV9zbWNjY19mZWF0dXJlcyBzbWNjY19mZWF0Ow0KPiAgCXN0cnVjdCBtYXBsZV90 cmVlIHNtY2NjX2ZpbHRlcjsNCj4gDQo+ICsJLyogRW11bGF0ZWQgQ1BVIElEIHJlZ2lzdGVycyAq Lw0KPiArCXN0cnVjdCBrdm1faWRyZWdzIGlkcmVnczsNCj4gKw0KPiAgCS8qDQo+ICAJICogRm9y IGFuIHVudHJ1c3RlZCBob3N0IFZNLCAncGt2bS5oYW5kbGUnIGlzIHVzZWQgdG8gbG9va3VwDQo+ ICAJICogdGhlIGFzc29jaWF0ZWQgcEtWTSBpbnN0YW5jZSBpbiB0aGUgaHlwZXJ2aXNvci4NCj4g QEAgLTEwNDUsNiArMTA2Myw4IEBAIGludCBrdm1fdm1faW9jdGxfbXRlX2NvcHlfdGFncyhzdHJ1 Y3Qga3ZtDQo+ICprdm0sDQo+ICBpbnQga3ZtX3ZtX2lvY3RsX3NldF9jb3VudGVyX29mZnNldChz dHJ1Y3Qga3ZtICprdm0sDQo+ICAJCQkJICAgIHN0cnVjdCBrdm1fYXJtX2NvdW50ZXJfb2Zmc2V0 ICpvZmZzZXQpOw0KPiANCj4gK3ZvaWQga3ZtX2FybV9pbml0X2lkX3JlZ3Moc3RydWN0IGt2bSAq a3ZtKTsNCj4gKw0KPiAgLyogR3Vlc3QvaG9zdCBGUFNJTUQgY29vcmRpbmF0aW9uIGhlbHBlcnMg Ki8NCj4gIGludCBrdm1fYXJjaF92Y3B1X3J1bl9tYXBfZnAoc3RydWN0IGt2bV92Y3B1ICp2Y3B1 KTsNCj4gIHZvaWQga3ZtX2FyY2hfdmNwdV9sb2FkX2ZwKHN0cnVjdCBrdm1fdmNwdSAqdmNwdSk7 DQo+IGRpZmYgLS1naXQgYS9hcmNoL2FybTY0L2t2bS9hcm0uYyBiL2FyY2gvYXJtNjQva3ZtL2Fy bS5jDQo+IGluZGV4IDE0MzkxODI2MjQxYy4uNzc0NjU2YTA3MThkIDEwMDY0NA0KPiAtLS0gYS9h cmNoL2FybTY0L2t2bS9hcm0uYw0KPiArKysgYi9hcmNoL2FybTY0L2t2bS9hcm0uYw0KPiBAQCAt MTYzLDYgKzE2Myw3IEBAIGludCBrdm1fYXJjaF9pbml0X3ZtKHN0cnVjdCBrdm0gKmt2bSwgdW5z aWduZWQNCj4gbG9uZyB0eXBlKQ0KPiANCj4gIAlzZXRfZGVmYXVsdF9zcGVjdHJlKGt2bSk7DQo+ ICAJa3ZtX2FybV9pbml0X2h5cGVyY2FsbHMoa3ZtKTsNCj4gKwlrdm1fYXJtX2luaXRfaWRfcmVn cyhrdm0pOw0KPiANCj4gIAkvKg0KPiAgCSAqIEluaXRpYWxpc2UgdGhlIGRlZmF1bHQgUE1VdmVy IGJlZm9yZSB0aGVyZSBpcyBhIGNoYW5jZSB0bw0KPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9r dm0vc3lzX3JlZ3MuYyBiL2FyY2gvYXJtNjQva3ZtL3N5c19yZWdzLmMNCj4gaW5kZXggNzFiMTIw OTRkNjEzLi5kMmVlM2ExYzdmMDMgMTAwNjQ0DQo+IC0tLSBhL2FyY2gvYXJtNjQva3ZtL3N5c19y ZWdzLmMNCj4gKysrIGIvYXJjaC9hcm02NC9rdm0vc3lzX3JlZ3MuYw0KPiBAQCAtNDEsNiArNDEs NyBAQA0KPiAgICogNjRiaXQgaW50ZXJmYWNlLg0KPiAgICovDQo+IA0KPiArc3RhdGljIHU2NCBr dm1fYXJtX3JlYWRfaWRfcmVnKGNvbnN0IHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwgdTMyIGlkKTsN Cj4gIHN0YXRpYyB1NjQgc3lzX3JlZ190b19pbmRleChjb25zdCBzdHJ1Y3Qgc3lzX3JlZ19kZXNj ICpyZWcpOw0KPiANCj4gIHN0YXRpYyBib29sIHJlYWRfZnJvbV93cml0ZV9vbmx5KHN0cnVjdCBr dm1fdmNwdSAqdmNwdSwNCj4gQEAgLTM2NCw3ICszNjUsNyBAQCBzdGF0aWMgYm9vbCB0cmFwX2xv cmVnaW9uKHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwNCj4gIAkJCSAgc3RydWN0IHN5c19yZWdfcGFy YW1zICpwLA0KPiAgCQkJICBjb25zdCBzdHJ1Y3Qgc3lzX3JlZ19kZXNjICpyKQ0KPiAgew0KPiAt CXU2NCB2YWwgPSByZWFkX3Nhbml0aXNlZF9mdHJfcmVnKFNZU19JRF9BQTY0TU1GUjFfRUwxKTsN Cj4gKwl1NjQgdmFsID0ga3ZtX2FybV9yZWFkX2lkX3JlZyh2Y3B1LCBTWVNfSURfQUE2NE1NRlIx X0VMMSk7DQo+ICAJdTMyIHNyID0gcmVnX3RvX2VuY29kaW5nKHIpOw0KPiANCj4gIAlpZiAoISh2 YWwgJiAoMHhmVUwgPDwgSURfQUE2NE1NRlIxX0VMMV9MT19TSElGVCkpKSB7DQo+IEBAIC0xMjA4 LDE2ICsxMjA5LDkgQEAgc3RhdGljIHU4IHBtdXZlcl90b19wZXJmbW9uKHU4IHBtdXZlcikNCj4g IAl9DQo+ICB9DQo+IA0KPiAtLyogUmVhZCBhIHNhbml0aXNlZCBjcHVmZWF0dXJlIElEIHJlZ2lz dGVyIGJ5IHN5c19yZWdfZGVzYyAqLw0KPiAtc3RhdGljIHU2NCByZWFkX2lkX3JlZyhjb25zdCBz dHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsIHN0cnVjdCBzeXNfcmVnX2Rlc2MNCj4gY29uc3QgKnIpDQo+ ICtzdGF0aWMgdTY0IGt2bV9hcm1fcmVhZF9pZF9yZWcoY29uc3Qgc3RydWN0IGt2bV92Y3B1ICp2 Y3B1LCB1MzIgaWQpDQo+ICB7DQo+IC0JdTMyIGlkID0gcmVnX3RvX2VuY29kaW5nKHIpOw0KPiAt CXU2NCB2YWw7DQo+IC0NCj4gLQlpZiAoc3lzcmVnX3Zpc2libGVfYXNfcmF6KHZjcHUsIHIpKQ0K PiAtCQlyZXR1cm4gMDsNCj4gLQ0KPiAtCXZhbCA9IHJlYWRfc2FuaXRpc2VkX2Z0cl9yZWcoaWQp Ow0KPiArCXU2NCB2YWwgPSBJRFJFRyh2Y3B1LT5rdm0sIGlkKTsNCj4gDQo+ICAJc3dpdGNoIChp ZCkgew0KPiAgCWNhc2UgU1lTX0lEX0FBNjRQRlIwX0VMMToNCj4gQEAgLTEyODAsNiArMTI3NCwy NiBAQCBzdGF0aWMgdTY0IHJlYWRfaWRfcmVnKGNvbnN0IHN0cnVjdCBrdm1fdmNwdQ0KPiAqdmNw dSwgc3RydWN0IHN5c19yZWdfZGVzYyBjb25zdCAqcg0KPiAgCXJldHVybiB2YWw7DQo+ICB9DQo+ IA0KPiArLyogUmVhZCBhIHNhbml0aXNlZCBjcHVmZWF0dXJlIElEIHJlZ2lzdGVyIGJ5IHN5c19y ZWdfZGVzYyAqLw0KPiArc3RhdGljIHU2NCByZWFkX2lkX3JlZyhjb25zdCBzdHJ1Y3Qga3ZtX3Zj cHUgKnZjcHUsIHN0cnVjdCBzeXNfcmVnX2Rlc2MNCj4gY29uc3QgKnIpDQo+ICt7DQo+ICsJaWYg KHN5c3JlZ192aXNpYmxlX2FzX3Jheih2Y3B1LCByKSkNCj4gKwkJcmV0dXJuIDA7DQo+ICsNCj4g KwlyZXR1cm4ga3ZtX2FybV9yZWFkX2lkX3JlZyh2Y3B1LCByZWdfdG9fZW5jb2RpbmcocikpOw0K PiArfQ0KPiArDQo+ICsvKg0KPiArICogUmV0dXJuIHRydWUgaWYgdGhlIHJlZ2lzdGVyJ3MgKE9w MCwgT3AxLCBDUm4sIENSbSwgT3AyKSBpcw0KPiArICogKDMsIDAsIDAsIGNybSwgb3AyKSwgd2hl cmUgMTw9Y3JtPDgsIDA8PW9wMjw4Lg0KPiArICovDQo+ICtzdGF0aWMgaW5saW5lIGJvb2wgaXNf aWRfcmVnKHUzMiBpZCkNCj4gK3sNCj4gKwlyZXR1cm4gKHN5c19yZWdfT3AwKGlkKSA9PSAzICYm IHN5c19yZWdfT3AxKGlkKSA9PSAwICYmDQo+ICsJCXN5c19yZWdfQ1JuKGlkKSA9PSAwICYmIHN5 c19yZWdfQ1JtKGlkKSA+PSAxICYmDQo+ICsJCXN5c19yZWdfQ1JtKGlkKSA8IDgpOw0KPiArfQ0K PiArDQo+ICBzdGF0aWMgdW5zaWduZWQgaW50IGlkX3Zpc2liaWxpdHkoY29uc3Qgc3RydWN0IGt2 bV92Y3B1ICp2Y3B1LA0KPiAgCQkJCSAgY29uc3Qgc3RydWN0IHN5c19yZWdfZGVzYyAqcikNCj4g IHsNCj4gQEAgLTIyNDQsOCArMjI1OCw4IEBAIHN0YXRpYyBib29sIHRyYXBfZGJnZGlkcihzdHJ1 Y3Qga3ZtX3ZjcHUgKnZjcHUsDQo+ICAJaWYgKHAtPmlzX3dyaXRlKSB7DQo+ICAJCXJldHVybiBp Z25vcmVfd3JpdGUodmNwdSwgcCk7DQo+ICAJfSBlbHNlIHsNCj4gLQkJdTY0IGRmciA9IHJlYWRf c2FuaXRpc2VkX2Z0cl9yZWcoU1lTX0lEX0FBNjRERlIwX0VMMSk7DQo+IC0JCXU2NCBwZnIgPSBy ZWFkX3Nhbml0aXNlZF9mdHJfcmVnKFNZU19JRF9BQTY0UEZSMF9FTDEpOw0KPiArCQl1NjQgZGZy ID0ga3ZtX2FybV9yZWFkX2lkX3JlZyh2Y3B1LCBTWVNfSURfQUE2NERGUjBfRUwxKTsNCj4gKwkJ dTY0IHBmciA9IGt2bV9hcm1fcmVhZF9pZF9yZWcodmNwdSwgU1lTX0lEX0FBNjRQRlIwX0VMMSk7 DQoNCkRvZXMgdGhpcyBjaGFuZ2UgdGhlIGJlaGF2aW9yIHNsaWdodGx5IGFzIG5vdyB3aXRoaW4g dGhlIGt2bV9hcm1fcmVhZF9pZF9yZWcoKQ0KdGhlIHZhbCB3aWxsIGJlIGZ1cnRoZXIgYWRqdXN0 ZWQgYmFzZWQgb24gS1ZNL3ZDUFU/DQoNClRoYW5rcywNClNoYW1lZXINCg0KPiAgCQl1MzIgZWwz ID0gISFjcHVpZF9mZWF0dXJlX2V4dHJhY3RfdW5zaWduZWRfZmllbGQocGZyLA0KPiBJRF9BQTY0 UEZSMF9FTDFfRUwzX1NISUZUKTsNCj4gDQo+ICAJCXAtPnJlZ3ZhbCA9ICgoKChkZnIgPj4gSURf QUE2NERGUjBfRUwxX1dSUHNfU0hJRlQpICYgMHhmKSA8PA0KPiAyOCkgfA0KPiBAQCAtMzM0Myw2 ICszMzU3LDM3IEBAIGludCBrdm1fYXJtX2NvcHlfc3lzX3JlZ19pbmRpY2VzKHN0cnVjdA0KPiBr dm1fdmNwdSAqdmNwdSwgdTY0IF9fdXNlciAqdWluZGljZXMpDQo+ICAJcmV0dXJuIHdyaXRlX2Rl bXV4X3JlZ2lkcyh1aW5kaWNlcyk7DQo+ICB9DQo+IA0KPiArLyoNCj4gKyAqIFNldCB0aGUgZ3Vl c3QncyBJRCByZWdpc3RlcnMgd2l0aCBJRF9TQU5JVElTRUQoKSB0byB0aGUgaG9zdCdzIHNhbml0 aXplZA0KPiB2YWx1ZS4NCj4gKyAqLw0KPiArdm9pZCBrdm1fYXJtX2luaXRfaWRfcmVncyhzdHJ1 Y3Qga3ZtICprdm0pDQo+ICt7DQo+ICsJY29uc3Qgc3RydWN0IHN5c19yZWdfZGVzYyAqaWRyZWc7 DQo+ICsJc3RydWN0IHN5c19yZWdfcGFyYW1zIHBhcmFtczsNCj4gKwl1MzIgaWQ7DQo+ICsNCj4g KwkvKiBGaW5kIHRoZSBmaXJzdCBpZHJlZyAoU1lTX0lEX1BGUjBfRUwxKSBpbiBzeXNfcmVnX2Rl c2NzLiAqLw0KPiArCWlkID0gU1lTX0lEX1BGUjBfRUwxOw0KPiArCXBhcmFtcyA9IGVuY29kaW5n X3RvX3BhcmFtcyhpZCk7DQo+ICsJaWRyZWcgPSBmaW5kX3JlZygmcGFyYW1zLCBzeXNfcmVnX2Rl c2NzLCBBUlJBWV9TSVpFKHN5c19yZWdfZGVzY3MpKTsNCj4gKwlpZiAoV0FSTl9PTighaWRyZWcp KQ0KPiArCQlyZXR1cm47DQo+ICsNCj4gKwkvKiBJbml0aWFsaXplIGFsbCBpZHJlZ3MgKi8NCj4g Kwl3aGlsZSAoaXNfaWRfcmVnKGlkKSkgew0KPiArCQkvKg0KPiArCQkgKiBTb21lIGhpZGRlbiBJ RCByZWdpc3RlcnMgd2hpY2ggYXJlIG5vdCBpbiBhcm02NF9mdHJfcmVnc1tdDQo+ICsJCSAqIHdv dWxkIGNhdXNlIHdhcm5pbmdzIGZyb20gcmVhZF9zYW5pdGlzZWRfZnRyX3JlZygpLg0KPiArCQkg KiBTa2lwIHRob3NlIElEIHJlZ2lzdGVycyB0byBhdm9pZCB0aGUgd2FybmluZ3MuDQo+ICsJCSAq Lw0KPiArCQlpZiAoaWRyZWctPnZpc2liaWxpdHkgIT0gcmF6X3Zpc2liaWxpdHkpDQo+ICsJCQlJ RFJFRyhrdm0sIGlkKSA9IHJlYWRfc2FuaXRpc2VkX2Z0cl9yZWcoaWQpOw0KPiArDQo+ICsJCWlk cmVnKys7DQo+ICsJCWlkID0gcmVnX3RvX2VuY29kaW5nKGlkcmVnKTsNCj4gKwl9DQo+ICt9DQo+ ICsNCj4gIGludCBfX2luaXQga3ZtX3N5c19yZWdfdGFibGVfaW5pdCh2b2lkKQ0KPiAgew0KPiAg CWJvb2wgdmFsaWQgPSB0cnVlOw0KPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9rdm0vc3lzX3Jl Z3MuaCBiL2FyY2gvYXJtNjQva3ZtL3N5c19yZWdzLmgNCj4gaW5kZXggNmIxMWYyY2M3MTQ2Li5l YmExMGRlMmU3YWUgMTAwNjQ0DQo+IC0tLSBhL2FyY2gvYXJtNjQva3ZtL3N5c19yZWdzLmgNCj4g KysrIGIvYXJjaC9hcm02NC9rdm0vc3lzX3JlZ3MuaA0KPiBAQCAtMjcsNiArMjcsMTMgQEAgc3Ry dWN0IHN5c19yZWdfcGFyYW1zIHsNCj4gIAlib29sCWlzX3dyaXRlOw0KPiAgfTsNCj4gDQo+ICsj ZGVmaW5lIGVuY29kaW5nX3RvX3BhcmFtcyhyZWcpCQkJCQkJXA0KPiArCSgoc3RydWN0IHN5c19y ZWdfcGFyYW1zKXsgLk9wMCA9IHN5c19yZWdfT3AwKHJlZyksCQlcDQo+ICsJCQkJICAuT3AxID0g c3lzX3JlZ19PcDEocmVnKSwJCVwNCj4gKwkJCQkgIC5DUm4gPSBzeXNfcmVnX0NSbihyZWcpLAkJ XA0KPiArCQkJCSAgLkNSbSA9IHN5c19yZWdfQ1JtKHJlZyksCQlcDQo+ICsJCQkJICAuT3AyID0g c3lzX3JlZ19PcDIocmVnKSB9KQ0KPiArDQo+ICAjZGVmaW5lIGVzcl9zeXM2NF90b19wYXJhbXMo ZXNyKQ0KPiBcDQo+ICAJKChzdHJ1Y3Qgc3lzX3JlZ19wYXJhbXMpeyAuT3AwID0gKChlc3IpID4+ IDIwKSAmIDMsDQo+IFwNCj4gIAkJCQkgIC5PcDEgPSAoKGVzcikgPj4gMTQpICYgMHg3LCAgICAg ICAgICAgICAgICAgIFwNCj4gLS0NCj4gMi40MC4xLjYwNi5nYTRiMWIxMjhkNi1nb29nDQo+IA0K DQo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40F51C77B7D for ; Thu, 18 May 2023 07:18:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pWOjP4wgnrWR0qKwSxgSZoUEehwuYmWJLlsuQX1txZQ=; b=LoIqDZZJBo8h5z pst4vqWnKysClUr7HVUmbrDvNnCBMHD1eGaPW4wDDwXbVUnG5FST7MBnqA2nsWQ2KzWLU2FbbMDtO 5YKO8SftQJex9J92BZTkxZvcGH+5M3k+MGJqN/OG90dYzIXll611ZOrEu+4wsRxUF+MdJl9B3iKsG AdRj7p8oWedBjwgoXC3YxaaOzC33rZj/l/O82TBTRda3yfZg7BMU80vCckz0Dh3/v7Bs5F+2twCj+ MVjMJoeTUna+q/GXZ2JjM4F5+LYT6+ZRcJ8H7fOHucETfw03FalQWAT+/HWWdQBVI0JR5oPRQKVeH pNmY46i2n9fYy5CZbiuQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzXtj-00CBjP-10; Thu, 18 May 2023 07:18:03 +0000 Received: from frasgout.his.huawei.com ([185.176.79.56]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzXtg-00CBhU-07 for linux-arm-kernel@lists.infradead.org; Thu, 18 May 2023 07:18:02 +0000 Received: from lhrpeml100001.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4QMLmX68xMz6J7Jm; Thu, 18 May 2023 15:13:32 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (7.191.163.240) by lhrpeml100001.china.huawei.com (7.191.160.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 18 May 2023 08:17:48 +0100 Received: from lhrpeml500005.china.huawei.com ([7.191.163.240]) by lhrpeml500005.china.huawei.com ([7.191.163.240]) with mapi id 15.01.2507.023; Thu, 18 May 2023 08:17:48 +0100 From: Shameerali Kolothum Thodi To: Jing Zhang , KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton CC: Will Deacon , Paolo Bonzini , "James Morse" , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta Subject: RE: [PATCH v9 1/5] KVM: arm64: Save ID registers' sanitized value per guest Thread-Topic: [PATCH v9 1/5] KVM: arm64: Save ID registers' sanitized value per guest Thread-Index: AQHZiIZI1S6VidLz8kuuQndld0olVq9fng1A Date: Thu, 18 May 2023 07:17:48 +0000 Message-ID: <2e727b02fe9141098ed474ef49ddc495@huawei.com> References: <20230517061015.1915934-1-jingzhangos@google.com> <20230517061015.1915934-2-jingzhangos@google.com> In-Reply-To: <20230517061015.1915934-2-jingzhangos@google.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.178] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_001800_383629_48216A9E X-CRM114-Status: GOOD ( 32.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Jing Zhang [mailto:jingzhangos@google.com] > Sent: 17 May 2023 07:10 > To: KVM ; KVMARM ; > ARMLinux ; Marc Zyngier > ; Oliver Upton > Cc: Will Deacon ; Paolo Bonzini ; > James Morse ; Alexandru Elisei > ; Suzuki K Poulose ; > Fuad Tabba ; Reiji Watanabe ; > Raghavendra Rao Ananta ; Jing Zhang > > Subject: [PATCH v9 1/5] KVM: arm64: Save ID registers' sanitized value per > guest > > Introduce id_regs[] in kvm_arch as a storage of guest's ID registers, > and save ID registers' sanitized value in the array at KVM_CREATE_VM. > Use the saved ones when ID registers are read by the guest or > userspace (via KVM_GET_ONE_REG). > > No functional change intended. > > Co-developed-by: Reiji Watanabe > Signed-off-by: Reiji Watanabe > Signed-off-by: Jing Zhang > --- > arch/arm64/include/asm/kvm_host.h | 20 +++++++++ > arch/arm64/kvm/arm.c | 1 + > arch/arm64/kvm/sys_regs.c | 69 > +++++++++++++++++++++++++------ > arch/arm64/kvm/sys_regs.h | 7 ++++ > 4 files changed, 85 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_host.h > b/arch/arm64/include/asm/kvm_host.h > index 7e7e19ef6993..949a4a782844 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -178,6 +178,21 @@ struct kvm_smccc_features { > unsigned long vendor_hyp_bmap; > }; > > +/* > + * Emulated CPU ID registers per VM > + * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it > + * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. > + * > + * These emulated idregs are VM-wide, but accessed from the context of a > vCPU. > + * Access to id regs are guarded by kvm_arch.config_lock. > + */ > +#define KVM_ARM_ID_REG_NUM 56 > +#define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) > +#define IDREG(kvm, id) ((kvm)->arch.idregs.regs[IDREG_IDX(id)]) > +struct kvm_idregs { > + u64 regs[KVM_ARM_ID_REG_NUM]; > +}; > Not sure we really need this struct here. Why can't this array be moved to struct kvm_arch directly? > typedef unsigned int pkvm_handle_t; > > struct kvm_protected_vm { > @@ -253,6 +268,9 @@ struct kvm_arch { > struct kvm_smccc_features smccc_feat; > struct maple_tree smccc_filter; > > + /* Emulated CPU ID registers */ > + struct kvm_idregs idregs; > + > /* > * For an untrusted host VM, 'pkvm.handle' is used to lookup > * the associated pKVM instance in the hypervisor. > @@ -1045,6 +1063,8 @@ int kvm_vm_ioctl_mte_copy_tags(struct kvm > *kvm, > int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, > struct kvm_arm_counter_offset *offset); > > +void kvm_arm_init_id_regs(struct kvm *kvm); > + > /* Guest/host FPSIMD coordination helpers */ > int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); > void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > index 14391826241c..774656a0718d 100644 > --- a/arch/arm64/kvm/arm.c > +++ b/arch/arm64/kvm/arm.c > @@ -163,6 +163,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned > long type) > > set_default_spectre(kvm); > kvm_arm_init_hypercalls(kvm); > + kvm_arm_init_id_regs(kvm); > > /* > * Initialise the default PMUver before there is a chance to > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 71b12094d613..d2ee3a1c7f03 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -41,6 +41,7 @@ > * 64bit interface. > */ > > +static u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id); > static u64 sys_reg_to_index(const struct sys_reg_desc *reg); > > static bool read_from_write_only(struct kvm_vcpu *vcpu, > @@ -364,7 +365,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, > struct sys_reg_params *p, > const struct sys_reg_desc *r) > { > - u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); > + u64 val = kvm_arm_read_id_reg(vcpu, SYS_ID_AA64MMFR1_EL1); > u32 sr = reg_to_encoding(r); > > if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { > @@ -1208,16 +1209,9 @@ static u8 pmuver_to_perfmon(u8 pmuver) > } > } > > -/* Read a sanitised cpufeature ID register by sys_reg_desc */ > -static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc > const *r) > +static u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id) > { > - u32 id = reg_to_encoding(r); > - u64 val; > - > - if (sysreg_visible_as_raz(vcpu, r)) > - return 0; > - > - val = read_sanitised_ftr_reg(id); > + u64 val = IDREG(vcpu->kvm, id); > > switch (id) { > case SYS_ID_AA64PFR0_EL1: > @@ -1280,6 +1274,26 @@ static u64 read_id_reg(const struct kvm_vcpu > *vcpu, struct sys_reg_desc const *r > return val; > } > > +/* Read a sanitised cpufeature ID register by sys_reg_desc */ > +static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc > const *r) > +{ > + if (sysreg_visible_as_raz(vcpu, r)) > + return 0; > + > + return kvm_arm_read_id_reg(vcpu, reg_to_encoding(r)); > +} > + > +/* > + * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is > + * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. > + */ > +static inline bool is_id_reg(u32 id) > +{ > + return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && > + sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && > + sys_reg_CRm(id) < 8); > +} > + > static unsigned int id_visibility(const struct kvm_vcpu *vcpu, > const struct sys_reg_desc *r) > { > @@ -2244,8 +2258,8 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu, > if (p->is_write) { > return ignore_write(vcpu, p); > } else { > - u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); > - u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); > + u64 dfr = kvm_arm_read_id_reg(vcpu, SYS_ID_AA64DFR0_EL1); > + u64 pfr = kvm_arm_read_id_reg(vcpu, SYS_ID_AA64PFR0_EL1); Does this change the behavior slightly as now within the kvm_arm_read_id_reg() the val will be further adjusted based on KVM/vCPU? Thanks, Shameer > u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, > ID_AA64PFR0_EL1_EL3_SHIFT); > > p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << > 28) | > @@ -3343,6 +3357,37 @@ int kvm_arm_copy_sys_reg_indices(struct > kvm_vcpu *vcpu, u64 __user *uindices) > return write_demux_regids(uindices); > } > > +/* > + * Set the guest's ID registers with ID_SANITISED() to the host's sanitized > value. > + */ > +void kvm_arm_init_id_regs(struct kvm *kvm) > +{ > + const struct sys_reg_desc *idreg; > + struct sys_reg_params params; > + u32 id; > + > + /* Find the first idreg (SYS_ID_PFR0_EL1) in sys_reg_descs. */ > + id = SYS_ID_PFR0_EL1; > + params = encoding_to_params(id); > + idreg = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); > + if (WARN_ON(!idreg)) > + return; > + > + /* Initialize all idregs */ > + while (is_id_reg(id)) { > + /* > + * Some hidden ID registers which are not in arm64_ftr_regs[] > + * would cause warnings from read_sanitised_ftr_reg(). > + * Skip those ID registers to avoid the warnings. > + */ > + if (idreg->visibility != raz_visibility) > + IDREG(kvm, id) = read_sanitised_ftr_reg(id); > + > + idreg++; > + id = reg_to_encoding(idreg); > + } > +} > + > int __init kvm_sys_reg_table_init(void) > { > bool valid = true; > diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h > index 6b11f2cc7146..eba10de2e7ae 100644 > --- a/arch/arm64/kvm/sys_regs.h > +++ b/arch/arm64/kvm/sys_regs.h > @@ -27,6 +27,13 @@ struct sys_reg_params { > bool is_write; > }; > > +#define encoding_to_params(reg) \ > + ((struct sys_reg_params){ .Op0 = sys_reg_Op0(reg), \ > + .Op1 = sys_reg_Op1(reg), \ > + .CRn = sys_reg_CRn(reg), \ > + .CRm = sys_reg_CRm(reg), \ > + .Op2 = sys_reg_Op2(reg) }) > + > #define esr_sys64_to_params(esr) > \ > ((struct sys_reg_params){ .Op0 = ((esr) >> 20) & 3, > \ > .Op1 = ((esr) >> 14) & 0x7, \ > -- > 2.40.1.606.ga4b1b128d6-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel