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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429c85ad08esm15687103f8f.19.2025.11.03.07.07.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Nov 2025 07:07:07 -0800 (PST) Message-ID: <2e8bd9fe-2434-443e-ae4e-e15352ff112a@redhat.com> Date: Mon, 3 Nov 2025 16:07:05 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 26/32] hw/arm/smmuv3-accel: Add a property to specify RIL support To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, kjaju@nvidia.com References: <20251031105005.24618-1-skolothumtho@nvidia.com> <20251031105005.24618-27-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: <20251031105005.24618-27-skolothumtho@nvidia.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: w-1_JOcmho9iphbR1q3db-fkIuPBZ8WzGTgkXiVEzjg_1762182431 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi Shameer, On 10/31/25 11:49 AM, Shameer Kolothum wrote: > Currently QEMU SMMUv3 has RIL support by default. But if accelerated mode > is enabled, RIL has to be compatible with host SMMUv3 support. > > Add a property so that the user can specify this. > > Reviewed-by: Jonathan Cameron > Tested-by: Zhangfei Gao > Signed-off-by: Shameer Kolothum I have not seen any reply on https://lore.kernel.org/all/b6105534-4a17-4700-bb0b-e961babd10bb@redhat.com/ I guess you chose to restrict RIL to accel only. About AIDR consistency check, did you have a look? Eric > --- > hw/arm/smmuv3-accel.c | 15 +++++++++++++-- > hw/arm/smmuv3-accel.h | 4 ++++ > hw/arm/smmuv3.c | 12 ++++++++++++ > include/hw/arm/smmuv3.h | 1 + > 4 files changed, 30 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index 8b9f88dd8e..35298350cb 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -63,10 +63,10 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, > return false; > } > > - /* QEMU SMMUv3 supports Range Invalidation by default */ > + /* User can disable QEMU SMMUv3 Range Invalidation support */ > if (FIELD_EX32(info->idr[3], IDR3, RIL) != > FIELD_EX32(s->idr[3], IDR3, RIL)) { > - error_setg(errp, "Host SMMUv3 doesn't support Range Invalidation"); > + error_setg(errp, "Host SMMUv3 differs in Range Invalidation support"); > return false; > } > > @@ -635,6 +635,17 @@ static const PCIIOMMUOps smmuv3_accel_ops = { > .get_msi_address_space = smmuv3_accel_get_msi_as, > }; > > +void smmuv3_accel_idr_override(SMMUv3State *s) > +{ > + if (!s->accel) { > + return; > + } > + > + /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it */ > + if (!s->ril) { > + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 0); > + } > +} > > /* Based on SMUUv3 GBPA configuration, attach a corresponding HWPT */ > void smmuv3_accel_gbpa_update(SMMUv3State *s) > diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h > index ee79548370..4f5b672712 100644 > --- a/hw/arm/smmuv3-accel.h > +++ b/hw/arm/smmuv3-accel.h > @@ -55,6 +55,7 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev, > Error **errp); > void smmuv3_accel_gbpa_update(SMMUv3State *s); > void smmuv3_accel_reset(SMMUv3State *s); > +void smmuv3_accel_idr_override(SMMUv3State *s); > #else > static inline void smmuv3_accel_init(SMMUv3State *s) > { > @@ -83,6 +84,9 @@ static inline void smmuv3_accel_gbpa_update(SMMUv3State *s) > static inline void smmuv3_accel_reset(SMMUv3State *s) > { > } > +static inline void smmuv3_accel_idr_override(SMMUv3State *s) > +{ > +} > #endif > > #endif /* HW_ARM_SMMUV3_ACCEL_H */ > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index f040e6b91e..b9d96f5762 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -305,6 +305,7 @@ static void smmuv3_init_id_regs(SMMUv3State *s) > s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); > s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); > s->aidr = 0x1; > + smmuv3_accel_idr_override(s); > } > > static void smmuv3_reset(SMMUv3State *s) > @@ -1936,6 +1937,13 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) > return false; > } > #endif > + if (!s->accel) { > + if (!s->ril) { > + error_setg(errp, "ril can only be disabled if accel=on"); > + return false; > + } > + return false; > + } > return true; > } > > @@ -2057,6 +2065,8 @@ static const Property smmuv3_properties[] = { > */ > DEFINE_PROP_STRING("stage", SMMUv3State, stage), > DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), > + /* RIL can be turned off for accel cases */ > + DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), > }; > > static void smmuv3_instance_init(Object *obj) > @@ -2084,6 +2094,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data) > "Enable SMMUv3 accelerator support." > "Allows host SMMUv3 to be configured " > "in nested mode for vfio-pci dev assignment"); > + object_class_property_set_description(klass, "ril", > + "Disable range invalidation support (for accel=on)"); > } > > static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, > diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h > index 6b9c27a9c4..95202c2757 100644 > --- a/include/hw/arm/smmuv3.h > +++ b/include/hw/arm/smmuv3.h > @@ -68,6 +68,7 @@ struct SMMUv3State { > bool accel; > struct SMMUv3AccelState *s_accel; > Error *migration_blocker; > + bool ril; > }; > > typedef enum {