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From: "Timur Kristóf" <timur.kristof@gmail.com>
To: "Christian König" <christian.koenig@amd.com>,
	amd-gfx@lists.freedesktop.org,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Alexandre Demers" <alexandre.f.demers@gmail.com>,
	"Rodrigo Siqueira" <siqueira@igalia.com>
Subject: Re: [PATCH 05/14] drm/amdgpu/vce: Clear VCPU BO before copying firmware to it
Date: Wed, 29 Oct 2025 11:48:41 +0100	[thread overview]
Message-ID: <2f0591f9dc2dadac72e8def5977afdc0a1e876b1.camel@gmail.com> (raw)
In-Reply-To: <baa0105d-3b37-4e63-8232-4f45976a3e7c@amd.com>

On Wed, 2025-10-29 at 11:19 +0100, Christian König wrote:
> On 10/28/25 23:06, Timur Kristóf wrote:
> > The VCPU BO doesn't only contain the VCE firmware but also other
> > ranges that the VCE uses for its stack and data. Let's initialize
> > this to zero to avoid having garbage in the VCPU BO.
> 
> Absolutely clear NAK.
> 
> This is intentionally not initialized on resume to avoid breaking
> encode sessions which existed before suspend.

How can there be encode sessions from before suspend?
I think that there can't be.

As far as I see, before suspend we wait for the VCE to go idle, meaning
that we wait for all pending work to finish.
amdgpu_vce_suspend has a comment which says:
suspending running encoding sessions isn't supported

> Why exactly is that an issue?

We need to clear at least some of the BO for the VCE1 firmware
validation mechanism. This is done in a memset in vce_v1_0_load_fw in
the old radeon driver.

Also I think it's a good idea to avoid having garbage in the VCPU BO.

> The VCE FW BO should be cleared to zero after initial allocation?

To clarify, are you suggesting that I move the memset to after the BO
creation, and then never clear it again? Or are you saying that
amdgpu_bo_create_reserved already clears the BO?

> 
> Regards,
> Christian.
> 
> > 
> > Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
> > Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> > index b9060bcd4806..eaa06dbef5c4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> > @@ -310,6 +310,7 @@ int amdgpu_vce_resume(struct amdgpu_device
> > *adev)
> >  	offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> >  
> >  	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
> > +		memset32(cpu_addr, 0, amdgpu_bo_size(adev-
> > >vce.vcpu_bo) / 4);
> >  		memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
> >  			    adev->vce.fw->size - offset);
> >  		drm_dev_exit(idx);

  reply	other threads:[~2025-10-29 10:48 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-28 22:06 [PATCH 00/14] drm/amdgpu: Support VCE1 IP block Timur Kristóf
2025-10-28 22:06 ` [PATCH 01/14] drm/amdgpu/gmc: Don't hardcode GART page count before GTT Timur Kristóf
2025-10-29 10:00   ` Christian König
2025-10-29 11:41     ` Timur Kristóf
2025-10-28 22:06 ` [PATCH 02/14] drm/amdgpu/gmc6: Place gart at low address range Timur Kristóf
2025-10-29 10:00   ` Christian König
2025-10-28 22:06 ` [PATCH 03/14] drm/amdgpu/gmc6: Add GART space for VCPU BO Timur Kristóf
2025-10-29 10:05   ` Christian König
2025-10-29 11:26     ` Timur Kristóf
2025-10-28 22:06 ` [PATCH 04/14] drm/amdgpu/gart: Add helper to bind VRAM BO Timur Kristóf
2025-10-29 10:16   ` Christian König
2025-10-29 10:57     ` Timur Kristóf
2025-10-28 22:06 ` [PATCH 05/14] drm/amdgpu/vce: Clear VCPU BO before copying firmware to it Timur Kristóf
2025-10-29 10:19   ` Christian König
2025-10-29 10:48     ` Timur Kristóf [this message]
2025-10-28 22:06 ` [PATCH 06/14] drm/amdgpu/vce: Move firmware load to amdgpu_vce_early_init Timur Kristóf
2025-10-29 10:26   ` Christian König
2025-10-29 17:16   ` Liu, Leo
2025-10-28 22:06 ` [PATCH 07/14] drm/amdgpu/si, cik, vi: Verify IP block when querying video codecs Timur Kristóf
2025-10-29 10:35   ` Christian König
2025-10-29 10:54     ` [PATCH 07/14] drm/amdgpu/si,cik,vi: " Timur Kristóf
2025-10-28 22:06 ` [PATCH 08/14] drm/amdgpu/vce1: Clean up register definitions Timur Kristóf
2025-10-29 11:23   ` Christian König
2025-10-28 22:06 ` [PATCH 09/14] drm/amdgpu/vce1: Load VCE1 firmware Timur Kristóf
2025-10-29 11:28   ` Christian König
2025-10-28 22:06 ` [PATCH 10/14] drm/amdgpu/vce1: Implement VCE1 IP block Timur Kristóf
2025-10-29 11:38   ` Christian König
2025-10-29 22:48     ` Timur Kristóf
2025-10-30 11:12       ` Christian König
2025-10-30 13:47         ` Timur Kristóf
2025-10-30 13:56           ` Christian König
2025-10-28 22:06 ` [PATCH 11/14] drm/amdgpu/vce1: Ensure VCPU BO is in lower 32-bit address space Timur Kristóf
2025-10-29 11:41   ` Christian König
2025-10-28 22:06 ` [PATCH 12/14] drm/amd/pm/si: Hook up VCE1 to SI DPM Timur Kristóf
2025-10-29 11:47   ` Christian König
2025-10-28 22:06 ` [PATCH 13/14] drm/amdgpu/vce1: Enable VCE1 on Tahiti, Pitcairn, Cape Verde GPUs Timur Kristóf
2025-10-29 11:51   ` Christian König
2025-10-28 22:06 ` [PATCH 14/14] drm/amdgpu/vce1: Tolerate VCE PLL timeout better Timur Kristóf
2025-10-29 12:02   ` Christian König
2025-10-29 19:46     ` Deucher, Alexander
2025-11-03 16:01       ` timur.kristof

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