diff for duplicates of <2f1c7dff-168e-4ad0-b426-cfe99fc33fd0@rivosinc.com>

diff --git a/a/1.txt b/N1/1.txt
index b975102..608d1a2 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -27,72 +27,72 @@ On 18/07/2024 18:43, Alexandre Ghiti wrote:
 >> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
 >> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 >> ---
->> ? arch/riscv/Kconfig?????????????? |? 1 +
->> ? arch/riscv/include/asm/csr.h???? |? 1 +
->> ? arch/riscv/include/asm/hwcap.h?? |? 2 ++
->> ? arch/riscv/include/asm/pgtable.h | 13 ++++++++++++-
->> ? arch/riscv/kernel/cpufeature.c?? | 32 ++++++++++++++++++++++++++++++++
->> ? 5 files changed, 48 insertions(+), 1 deletion(-)
+>>   arch/riscv/Kconfig               |  1 +
+>>   arch/riscv/include/asm/csr.h     |  1 +
+>>   arch/riscv/include/asm/hwcap.h   |  2 ++
+>>   arch/riscv/include/asm/pgtable.h | 13 ++++++++++++-
+>>   arch/riscv/kernel/cpufeature.c   | 32 ++++++++++++++++++++++++++++++++
+>>   5 files changed, 48 insertions(+), 1 deletion(-)
 >>
 >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
 >> index 0525ee2d63c7..3d705e28ff85 100644
 >> --- a/arch/riscv/Kconfig
 >> +++ b/arch/riscv/Kconfig
 >> @@ -36,6 +36,7 @@ config RISCV
->> ????? select ARCH_HAS_PMEM_API
->> ????? select ARCH_HAS_PREPARE_SYNC_CORE_CMD
->> ????? select ARCH_HAS_PTE_SPECIAL
->> +??? select ARCH_HAS_HW_PTE_YOUNG
->> ????? select ARCH_HAS_SET_DIRECT_MAP if MMU
->> ????? select ARCH_HAS_SET_MEMORY if MMU
->> ????? select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
+>>       select ARCH_HAS_PMEM_API
+>>       select ARCH_HAS_PREPARE_SYNC_CORE_CMD
+>>       select ARCH_HAS_PTE_SPECIAL
+>> +    select ARCH_HAS_HW_PTE_YOUNG
+>>       select ARCH_HAS_SET_DIRECT_MAP if MMU
+>>       select ARCH_HAS_SET_MEMORY if MMU
+>>       select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
 >> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
 >> index 25966995da04..524cd4131c71 100644
 >> --- a/arch/riscv/include/asm/csr.h
 >> +++ b/arch/riscv/include/asm/csr.h
 >> @@ -195,6 +195,7 @@
->> ? /* xENVCFG flags */
->> ? #define ENVCFG_STCE??????????? (_AC(1, ULL) << 63)
->> ? #define ENVCFG_PBMTE??????????? (_AC(1, ULL) << 62)
->> +#define ENVCFG_ADUE??????????? (_AC(1, ULL) << 61)
->> ? #define ENVCFG_CBZE??????????? (_AC(1, UL) << 7)
->> ? #define ENVCFG_CBCFE??????????? (_AC(1, UL) << 6)
->> ? #define ENVCFG_CBIE_SHIFT??????? 4
+>>   /* xENVCFG flags */
+>>   #define ENVCFG_STCE            (_AC(1, ULL) << 63)
+>>   #define ENVCFG_PBMTE            (_AC(1, ULL) << 62)
+>> +#define ENVCFG_ADUE            (_AC(1, ULL) << 61)
+>>   #define ENVCFG_CBZE            (_AC(1, UL) << 7)
+>>   #define ENVCFG_CBCFE            (_AC(1, UL) << 6)
+>>   #define ENVCFG_CBIE_SHIFT        4
 >> diff --git a/arch/riscv/include/asm/hwcap.h
 >> b/arch/riscv/include/asm/hwcap.h
 >> index e17d0078a651..35d7aa49785d 100644
 >> --- a/arch/riscv/include/asm/hwcap.h
 >> +++ b/arch/riscv/include/asm/hwcap.h
 >> @@ -81,6 +81,8 @@
->> ? #define RISCV_ISA_EXT_ZTSO??????? 72
->> ? #define RISCV_ISA_EXT_ZACAS??????? 73
->> ? #define RISCV_ISA_EXT_XANDESPMU??????? 74
->> +#define RISCV_ISA_EXT_SVADE???????????? 75
->> +#define RISCV_ISA_EXT_SVADU??????? 76
->> ? ? #define RISCV_ISA_EXT_XLINUXENVCFG??? 127
->> ? diff --git a/arch/riscv/include/asm/pgtable.h
+>>   #define RISCV_ISA_EXT_ZTSO        72
+>>   #define RISCV_ISA_EXT_ZACAS        73
+>>   #define RISCV_ISA_EXT_XANDESPMU        74
+>> +#define RISCV_ISA_EXT_SVADE             75
+>> +#define RISCV_ISA_EXT_SVADU        76
+>>     #define RISCV_ISA_EXT_XLINUXENVCFG    127
+>>   diff --git a/arch/riscv/include/asm/pgtable.h
 >> b/arch/riscv/include/asm/pgtable.h
 >> index aad8b8ca51f1..ec0cdacd7da0 100644
 >> --- a/arch/riscv/include/asm/pgtable.h
 >> +++ b/arch/riscv/include/asm/pgtable.h
 >> @@ -120,6 +120,7 @@
->> ? #include <asm/tlbflush.h>
->> ? #include <linux/mm_types.h>
->> ? #include <asm/compat.h>
+>>   #include <asm/tlbflush.h>
+>>   #include <linux/mm_types.h>
+>>   #include <asm/compat.h>
 >> +#include <asm/cpufeature.h>
->> ? ? #define __page_val_to_pfn(_val)? (((_val) & _PAGE_PFN_MASK) >>
+>>     #define __page_val_to_pfn(_val)  (((_val) & _PAGE_PFN_MASK) >>
 >> _PAGE_PFN_SHIFT)
->> ? @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud)
->> ? }
->> ? ? #ifdef CONFIG_RISCV_ISA_SVNAPOT
+>>   @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud)
+>>   }
+>>     #ifdef CONFIG_RISCV_ISA_SVNAPOT
 >> -#include <asm/cpufeature.h>
->> ? ? static __always_inline bool has_svnapot(void)
->> ? {
+>>     static __always_inline bool has_svnapot(void)
+>>   {
 >> @@ -624,6 +624,17 @@ static inline pgprot_t
 >> pgprot_writecombine(pgprot_t _prot)
->> ????? return __pgprot(prot);
->> ? }
->> ? +/*
+>>       return __pgprot(prot);
+>>   }
+>>   +/*
 >> + * Both Svade and Svadu control the hardware behavior when the PTE
 >> A/D bits need to be set. By
 >> + * default the M-mode firmware enables the hardware updating scheme
@@ -102,75 +102,75 @@ On 18/07/2024 18:43, Alexandre Ghiti wrote:
 >> +#define arch_has_hw_pte_young arch_has_hw_pte_young
 >> +static inline bool arch_has_hw_pte_young(void)
 >> +{
->> +??? return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
+>> +    return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
 >> +}
 >> +
->> ? /*
->> ?? * THP functions
->> ?? */
+>>   /*
+>>    * THP functions
+>>    */
 >> diff --git a/arch/riscv/kernel/cpufeature.c
 >> b/arch/riscv/kernel/cpufeature.c
 >> index 5ef48cb20ee1..b2c3fe945e89 100644
 >> --- a/arch/riscv/kernel/cpufeature.c
 >> +++ b/arch/riscv/kernel/cpufeature.c
 >> @@ -301,6 +301,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
->> ????? __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
->> ????? __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
->> ????? __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
->> +??? __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
->> +??? __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU),
->> ????? __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
->> ????? __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
->> ????? __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
+>>       __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
+>>       __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
+>>       __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
+>> +    __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
+>> +    __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU),
+>>       __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
+>>       __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
+>>       __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
 >> @@ -554,6 +556,21 @@ static void __init
 >> riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
->> ????????????? clear_bit(RISCV_ISA_EXT_v, isainfo->isa);
->> ????????? }
->> ? +??????? /*
->> +???????? * When neither Svade nor Svadu present in DT, it is technically
->> +???????? * unknown whether the platform uses Svade or Svadu.
+>>               clear_bit(RISCV_ISA_EXT_v, isainfo->isa);
+>>           }
+>>   +        /*
+>> +         * When neither Svade nor Svadu present in DT, it is technically
+>> +         * unknown whether the platform uses Svade or Svadu.
 >> Supervisor may
->> +???????? * assume Svade to be present and enabled or it can discover
+>> +         * assume Svade to be present and enabled or it can discover
 >> based
->> +???????? * on mvendorid, marchid, and mimpid. When both Svade and
+>> +         * on mvendorid, marchid, and mimpid. When both Svade and
 >> Svadu present
->> +???????? * in DT, supervisor must assume Svadu turned-off at boot
+>> +         * in DT, supervisor must assume Svadu turned-off at boot
 >> time. To use
->> +???????? * Svadu, supervisor must explicitly enable it using the SBI
+>> +         * Svadu, supervisor must explicitly enable it using the SBI
 >> FWFT extension.
->> +???????? */
->> +??????? if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&
->> +??????????? !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))
->> +??????????? set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa);
->> +??????? else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&
->> +???????????? test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))
->> +??????????? clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa);
+>> +         */
+>> +        if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&
+>> +            !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))
+>> +            set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa);
+>> +        else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&
+>> +             test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))
+>> +            clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa);
 >> +
->> ????????? /*
->> ?????????? * All "okay" hart should have same isa. Set HWCAP based on
->> ?????????? * common capabilities of every "okay" hart, in case they don't
+>>           /*
+>>            * All "okay" hart should have same isa. Set HWCAP based on
+>>            * common capabilities of every "okay" hart, in case they don't
 >> @@ -619,6 +636,21 @@ static int __init
 >> riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
->> ? ????????? of_node_put(cpu_node);
->> ? +??????? /*
->> +???????? * When neither Svade nor Svadu present in DT, it is technically
->> +???????? * unknown whether the platform uses Svade or Svadu.
+>>             of_node_put(cpu_node);
+>>   +        /*
+>> +         * When neither Svade nor Svadu present in DT, it is technically
+>> +         * unknown whether the platform uses Svade or Svadu.
 >> Supervisor may
->> +???????? * assume Svade to be present and enabled or it can discover
+>> +         * assume Svade to be present and enabled or it can discover
 >> based
->> +???????? * on mvendorid, marchid, and mimpid. When both Svade and
+>> +         * on mvendorid, marchid, and mimpid. When both Svade and
 >> Svadu present
->> +???????? * in DT, supervisor must assume Svadu turned-off at boot
+>> +         * in DT, supervisor must assume Svadu turned-off at boot
 >> time. To use
->> +???????? * Svadu, supervisor must explicitly enable it using the SBI
+>> +         * Svadu, supervisor must explicitly enable it using the SBI
 >> FWFT extension.
->> +???????? */
->> +??????? if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&
->> +??????????? !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))
->> +??????????? set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa);
->> +??????? else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&
->> +???????????? test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))
->> +??????????? clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa);
+>> +         */
+>> +        if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&
+>> +            !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))
+>> +            set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa);
+>> +        else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&
+>> +             test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))
+>> +            clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa);
 >> +
 
 This is a duplicate of the previous chunk of code. Moreover, now that we
@@ -206,13 +206,13 @@ in your patch series, I think it is sane to keep it like that.
 
 Thanks,
 
-Cl?ment
+Clément
 
 
 
->> ????????? /*
->> ?????????? * All "okay" harts should have same isa. Set HWCAP based on
->> ?????????? * common capabilities of every "okay" hart, in case they
+>>           /*
+>>            * All "okay" harts should have same isa. Set HWCAP based on
+>>            * common capabilities of every "okay" hart, in case they
 >> don't.
 > 
 > 
@@ -221,4 +221,9 @@ Cl?ment
 > Thanks,
 > 
 > Alex
->
+> 
+
+_______________________________________________
+linux-riscv mailing list
+linux-riscv@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/a/content_digest b/N1/content_digest
index 5136de4..d4d8962 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,9 +2,38 @@
  "ref\020240712083850.4242-2-yongxuan.wang@sifive.com\0"
  "ref\06ad0c386-6777-4467-bab4-8fba149f3bfe@ghiti.fr\0"
  "From\0Cl\303\251ment L\303\251ger <cleger@rivosinc.com>\0"
- "Subject\0[PATCH v7 1/4] RISC-V: Add Svade and Svadu Extensions Support\0"
+ "Subject\0Re: [PATCH v7 1/4] RISC-V: Add Svade and Svadu Extensions Support\0"
  "Date\0Fri, 19 Jul 2024 09:38:04 +0200\0"
- "To\0kvm-riscv@lists.infradead.org\0"
+ "To\0Alexandre Ghiti <alex@ghiti.fr>"
+  Yong-Xuan Wang <yongxuan.wang@sifive.com>
+  linux-kernel@vger.kernel.org
+  linux-riscv@lists.infradead.org
+  kvm-riscv@lists.infradead.org
+ " kvm@vger.kernel.org\0"
+ "Cc\0greentime.hu@sifive.com"
+  vincent.chen@sifive.com
+  Jinyu Tang <tjytimi@163.com>
+  Paul Walmsley <paul.walmsley@sifive.com>
+  Palmer Dabbelt <palmer@dabbelt.com>
+  Albert Ou <aou@eecs.berkeley.edu>
+  Andrew Jones <ajones@ventanamicro.com>
+  Anup Patel <anup@brainfault.org>
+  Conor Dooley <conor.dooley@microchip.com>
+  Mayuresh Chitale <mchitale@ventanamicro.com>
+  Atish Patra <atishp@rivosinc.com>
+  Samuel Ortiz <sameo@rivosinc.com>
+  Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+  Samuel Holland <samuel.holland@sifive.com>
+  Evan Green <evan@rivosinc.com>
+  Xiao Wang <xiao.w.wang@intel.com>
+  Alexandre Ghiti <alexghiti@rivosinc.com>
+  Andrew Morton <akpm@linux-foundation.org>
+  Kemeng Shi <shikemeng@huaweicloud.com>
+  Mike Rapoport (IBM) <rppt@kernel.org>
+  Leonardo Bras <leobras@redhat.com>
+  Charlie Jenkins <charlie@rivosinc.com>
+  Matthew Wilcox (Oracle) <willy@infradead.org>
+ " Jisheng Zhang <jszhang@kernel.org>\0"
  "\00:1\0"
  "b\0"
  "\n"
@@ -36,72 +65,72 @@
  ">> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>\n"
  ">> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>\n"
  ">> ---\n"
- ">> ? arch/riscv/Kconfig?????????????? |? 1 +\n"
- ">> ? arch/riscv/include/asm/csr.h???? |? 1 +\n"
- ">> ? arch/riscv/include/asm/hwcap.h?? |? 2 ++\n"
- ">> ? arch/riscv/include/asm/pgtable.h | 13 ++++++++++++-\n"
- ">> ? arch/riscv/kernel/cpufeature.c?? | 32 ++++++++++++++++++++++++++++++++\n"
- ">> ? 5 files changed, 48 insertions(+), 1 deletion(-)\n"
+ ">> \302\240 arch/riscv/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240 1 +\n"
+ ">> \302\240 arch/riscv/include/asm/csr.h\302\240\302\240\302\240\302\240 |\302\240 1 +\n"
+ ">> \302\240 arch/riscv/include/asm/hwcap.h\302\240\302\240 |\302\240 2 ++\n"
+ ">> \302\240 arch/riscv/include/asm/pgtable.h | 13 ++++++++++++-\n"
+ ">> \302\240 arch/riscv/kernel/cpufeature.c\302\240\302\240 | 32 ++++++++++++++++++++++++++++++++\n"
+ ">> \302\240 5 files changed, 48 insertions(+), 1 deletion(-)\n"
  ">>\n"
  ">> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig\n"
  ">> index 0525ee2d63c7..3d705e28ff85 100644\n"
  ">> --- a/arch/riscv/Kconfig\n"
  ">> +++ b/arch/riscv/Kconfig\n"
  ">> @@ -36,6 +36,7 @@ config RISCV\n"
- ">> ????? select ARCH_HAS_PMEM_API\n"
- ">> ????? select ARCH_HAS_PREPARE_SYNC_CORE_CMD\n"
- ">> ????? select ARCH_HAS_PTE_SPECIAL\n"
- ">> +??? select ARCH_HAS_HW_PTE_YOUNG\n"
- ">> ????? select ARCH_HAS_SET_DIRECT_MAP if MMU\n"
- ">> ????? select ARCH_HAS_SET_MEMORY if MMU\n"
- ">> ????? select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 select ARCH_HAS_PMEM_API\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 select ARCH_HAS_PREPARE_SYNC_CORE_CMD\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 select ARCH_HAS_PTE_SPECIAL\n"
+ ">> +\302\240\302\240\302\240 select ARCH_HAS_HW_PTE_YOUNG\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 select ARCH_HAS_SET_DIRECT_MAP if MMU\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 select ARCH_HAS_SET_MEMORY if MMU\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL\n"
  ">> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h\n"
  ">> index 25966995da04..524cd4131c71 100644\n"
  ">> --- a/arch/riscv/include/asm/csr.h\n"
  ">> +++ b/arch/riscv/include/asm/csr.h\n"
  ">> @@ -195,6 +195,7 @@\n"
- ">> ? /* xENVCFG flags */\n"
- ">> ? #define ENVCFG_STCE??????????? (_AC(1, ULL) << 63)\n"
- ">> ? #define ENVCFG_PBMTE??????????? (_AC(1, ULL) << 62)\n"
- ">> +#define ENVCFG_ADUE??????????? (_AC(1, ULL) << 61)\n"
- ">> ? #define ENVCFG_CBZE??????????? (_AC(1, UL) << 7)\n"
- ">> ? #define ENVCFG_CBCFE??????????? (_AC(1, UL) << 6)\n"
- ">> ? #define ENVCFG_CBIE_SHIFT??????? 4\n"
+ ">> \302\240 /* xENVCFG flags */\n"
+ ">> \302\240 #define ENVCFG_STCE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 (_AC(1, ULL) << 63)\n"
+ ">> \302\240 #define ENVCFG_PBMTE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 (_AC(1, ULL) << 62)\n"
+ ">> +#define ENVCFG_ADUE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 (_AC(1, ULL) << 61)\n"
+ ">> \302\240 #define ENVCFG_CBZE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 (_AC(1, UL) << 7)\n"
+ ">> \302\240 #define ENVCFG_CBCFE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 (_AC(1, UL) << 6)\n"
+ ">> \302\240 #define ENVCFG_CBIE_SHIFT\302\240\302\240\302\240\302\240\302\240\302\240\302\240 4\n"
  ">> diff --git a/arch/riscv/include/asm/hwcap.h\n"
  ">> b/arch/riscv/include/asm/hwcap.h\n"
  ">> index e17d0078a651..35d7aa49785d 100644\n"
  ">> --- a/arch/riscv/include/asm/hwcap.h\n"
  ">> +++ b/arch/riscv/include/asm/hwcap.h\n"
  ">> @@ -81,6 +81,8 @@\n"
- ">> ? #define RISCV_ISA_EXT_ZTSO??????? 72\n"
- ">> ? #define RISCV_ISA_EXT_ZACAS??????? 73\n"
- ">> ? #define RISCV_ISA_EXT_XANDESPMU??????? 74\n"
- ">> +#define RISCV_ISA_EXT_SVADE???????????? 75\n"
- ">> +#define RISCV_ISA_EXT_SVADU??????? 76\n"
- ">> ? ? #define RISCV_ISA_EXT_XLINUXENVCFG??? 127\n"
- ">> ? diff --git a/arch/riscv/include/asm/pgtable.h\n"
+ ">> \302\240 #define RISCV_ISA_EXT_ZTSO\302\240\302\240\302\240\302\240\302\240\302\240\302\240 72\n"
+ ">> \302\240 #define RISCV_ISA_EXT_ZACAS\302\240\302\240\302\240\302\240\302\240\302\240\302\240 73\n"
+ ">> \302\240 #define RISCV_ISA_EXT_XANDESPMU\302\240\302\240\302\240\302\240\302\240\302\240\302\240 74\n"
+ ">> +#define RISCV_ISA_EXT_SVADE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 75\n"
+ ">> +#define RISCV_ISA_EXT_SVADU\302\240\302\240\302\240\302\240\302\240\302\240\302\240 76\n"
+ ">> \302\240 \302\240 #define RISCV_ISA_EXT_XLINUXENVCFG\302\240\302\240\302\240 127\n"
+ ">> \302\240 diff --git a/arch/riscv/include/asm/pgtable.h\n"
  ">> b/arch/riscv/include/asm/pgtable.h\n"
  ">> index aad8b8ca51f1..ec0cdacd7da0 100644\n"
  ">> --- a/arch/riscv/include/asm/pgtable.h\n"
  ">> +++ b/arch/riscv/include/asm/pgtable.h\n"
  ">> @@ -120,6 +120,7 @@\n"
- ">> ? #include <asm/tlbflush.h>\n"
- ">> ? #include <linux/mm_types.h>\n"
- ">> ? #include <asm/compat.h>\n"
+ ">> \302\240 #include <asm/tlbflush.h>\n"
+ ">> \302\240 #include <linux/mm_types.h>\n"
+ ">> \302\240 #include <asm/compat.h>\n"
  ">> +#include <asm/cpufeature.h>\n"
- ">> ? ? #define __page_val_to_pfn(_val)? (((_val) & _PAGE_PFN_MASK) >>\n"
+ ">> \302\240 \302\240 #define __page_val_to_pfn(_val)\302\240 (((_val) & _PAGE_PFN_MASK) >>\n"
  ">> _PAGE_PFN_SHIFT)\n"
- ">> ? @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud)\n"
- ">> ? }\n"
- ">> ? ? #ifdef CONFIG_RISCV_ISA_SVNAPOT\n"
+ ">> \302\240 @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud)\n"
+ ">> \302\240 }\n"
+ ">> \302\240 \302\240 #ifdef CONFIG_RISCV_ISA_SVNAPOT\n"
  ">> -#include <asm/cpufeature.h>\n"
- ">> ? ? static __always_inline bool has_svnapot(void)\n"
- ">> ? {\n"
+ ">> \302\240 \302\240 static __always_inline bool has_svnapot(void)\n"
+ ">> \302\240 {\n"
  ">> @@ -624,6 +624,17 @@ static inline pgprot_t\n"
  ">> pgprot_writecombine(pgprot_t _prot)\n"
- ">> ????? return __pgprot(prot);\n"
- ">> ? }\n"
- ">> ? +/*\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 return __pgprot(prot);\n"
+ ">> \302\240 }\n"
+ ">> \302\240 +/*\n"
  ">> + * Both Svade and Svadu control the hardware behavior when the PTE\n"
  ">> A/D bits need to be set. By\n"
  ">> + * default the M-mode firmware enables the hardware updating scheme\n"
@@ -111,75 +140,75 @@
  ">> +#define arch_has_hw_pte_young arch_has_hw_pte_young\n"
  ">> +static inline bool arch_has_hw_pte_young(void)\n"
  ">> +{\n"
- ">> +??? return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);\n"
+ ">> +\302\240\302\240\302\240 return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);\n"
  ">> +}\n"
  ">> +\n"
- ">> ? /*\n"
- ">> ?? * THP functions\n"
- ">> ?? */\n"
+ ">> \302\240 /*\n"
+ ">> \302\240\302\240 * THP functions\n"
+ ">> \302\240\302\240 */\n"
  ">> diff --git a/arch/riscv/kernel/cpufeature.c\n"
  ">> b/arch/riscv/kernel/cpufeature.c\n"
  ">> index 5ef48cb20ee1..b2c3fe945e89 100644\n"
  ">> --- a/arch/riscv/kernel/cpufeature.c\n"
  ">> +++ b/arch/riscv/kernel/cpufeature.c\n"
  ">> @@ -301,6 +301,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {\n"
- ">> ????? __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),\n"
- ">> ????? __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),\n"
- ">> ????? __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),\n"
- ">> +??? __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),\n"
- ">> +??? __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU),\n"
- ">> ????? __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),\n"
- ">> ????? __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),\n"
- ">> ????? __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),\n"
+ ">> +\302\240\302\240\302\240 __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),\n"
+ ">> +\302\240\302\240\302\240 __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU),\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),\n"
+ ">> \302\240\302\240\302\240\302\240\302\240 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),\n"
  ">> @@ -554,6 +556,21 @@ static void __init\n"
  ">> riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)\n"
- ">> ????????????? clear_bit(RISCV_ISA_EXT_v, isainfo->isa);\n"
- ">> ????????? }\n"
- ">> ? +??????? /*\n"
- ">> +???????? * When neither Svade nor Svadu present in DT, it is technically\n"
- ">> +???????? * unknown whether the platform uses Svade or Svadu.\n"
+ ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 clear_bit(RISCV_ISA_EXT_v, isainfo->isa);\n"
+ ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 }\n"
+ ">> \302\240 +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 /*\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * When neither Svade nor Svadu present in DT, it is technically\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * unknown whether the platform uses Svade or Svadu.\n"
  ">> Supervisor may\n"
- ">> +???????? * assume Svade to be present and enabled or it can discover\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * assume Svade to be present and enabled or it can discover\n"
  ">> based\n"
- ">> +???????? * on mvendorid, marchid, and mimpid. When both Svade and\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * on mvendorid, marchid, and mimpid. When both Svade and\n"
  ">> Svadu present\n"
- ">> +???????? * in DT, supervisor must assume Svadu turned-off at boot\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * in DT, supervisor must assume Svadu turned-off at boot\n"
  ">> time. To use\n"
- ">> +???????? * Svadu, supervisor must explicitly enable it using the SBI\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * Svadu, supervisor must explicitly enable it using the SBI\n"
  ">> FWFT extension.\n"
- ">> +???????? */\n"
- ">> +??????? if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&\n"
- ">> +??????????? !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))\n"
- ">> +??????????? set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa);\n"
- ">> +??????? else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&\n"
- ">> +???????????? test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))\n"
- ">> +??????????? clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa);\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa);\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa);\n"
  ">> +\n"
- ">> ????????? /*\n"
- ">> ?????????? * All \"okay\" hart should have same isa. Set HWCAP based on\n"
- ">> ?????????? * common capabilities of every \"okay\" hart, in case they don't\n"
+ ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 /*\n"
+ ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * All \"okay\" hart should have same isa. Set HWCAP based on\n"
+ ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * common capabilities of every \"okay\" hart, in case they don't\n"
  ">> @@ -619,6 +636,21 @@ static int __init\n"
  ">> riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)\n"
- ">> ? ????????? of_node_put(cpu_node);\n"
- ">> ? +??????? /*\n"
- ">> +???????? * When neither Svade nor Svadu present in DT, it is technically\n"
- ">> +???????? * unknown whether the platform uses Svade or Svadu.\n"
+ ">> \302\240 \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 of_node_put(cpu_node);\n"
+ ">> \302\240 +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 /*\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * When neither Svade nor Svadu present in DT, it is technically\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * unknown whether the platform uses Svade or Svadu.\n"
  ">> Supervisor may\n"
- ">> +???????? * assume Svade to be present and enabled or it can discover\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * assume Svade to be present and enabled or it can discover\n"
  ">> based\n"
- ">> +???????? * on mvendorid, marchid, and mimpid. When both Svade and\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * on mvendorid, marchid, and mimpid. When both Svade and\n"
  ">> Svadu present\n"
- ">> +???????? * in DT, supervisor must assume Svadu turned-off at boot\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * in DT, supervisor must assume Svadu turned-off at boot\n"
  ">> time. To use\n"
- ">> +???????? * Svadu, supervisor must explicitly enable it using the SBI\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * Svadu, supervisor must explicitly enable it using the SBI\n"
  ">> FWFT extension.\n"
- ">> +???????? */\n"
- ">> +??????? if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&\n"
- ">> +??????????? !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))\n"
- ">> +??????????? set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa);\n"
- ">> +??????? else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&\n"
- ">> +???????????? test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))\n"
- ">> +??????????? clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa);\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa);\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) &&\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa))\n"
+ ">> +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa);\n"
  ">> +\n"
  "\n"
  "This is a duplicate of the previous chunk of code. Moreover, now that we\n"
@@ -215,13 +244,13 @@
  "\n"
  "Thanks,\n"
  "\n"
- "Cl?ment\n"
+ "Cl\303\251ment\n"
  "\n"
  "\n"
  "\n"
- ">> ????????? /*\n"
- ">> ?????????? * All \"okay\" harts should have same isa. Set HWCAP based on\n"
- ">> ?????????? * common capabilities of every \"okay\" hart, in case they\n"
+ ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 /*\n"
+ ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * All \"okay\" harts should have same isa. Set HWCAP based on\n"
+ ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * common capabilities of every \"okay\" hart, in case they\n"
  ">> don't.\n"
  "> \n"
  "> \n"
@@ -230,6 +259,11 @@
  "> Thanks,\n"
  "> \n"
  "> Alex\n"
- >
+ "> \n"
+ "\n"
+ "_______________________________________________\n"
+ "linux-riscv mailing list\n"
+ "linux-riscv@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-riscv
 
-f819cde2730614b60577706e158544787248cf999a23cb726d5c5e4577982781
+459c16717021240b1b6a5e949e50850c968c590fde3c92de6784ebfde8f2f8b7
