From mboxrd@z Thu Jan 1 00:00:00 1970 From: Clément Léger Date: Fri, 19 Jul 2024 09:38:04 +0200 Subject: [PATCH v7 1/4] RISC-V: Add Svade and Svadu Extensions Support In-Reply-To: <6ad0c386-6777-4467-bab4-8fba149f3bfe@ghiti.fr> References: <20240712083850.4242-1-yongxuan.wang@sifive.com> <20240712083850.4242-2-yongxuan.wang@sifive.com> <6ad0c386-6777-4467-bab4-8fba149f3bfe@ghiti.fr> Message-ID: <2f1c7dff-168e-4ad0-b426-cfe99fc33fd0@rivosinc.com> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hi Yong-Xuan, On 18/07/2024 18:43, Alexandre Ghiti wrote: > Hi Yong-Xuan, > > On 12/07/2024 10:38, Yong-Xuan Wang wrote: >> Svade and Svadu extensions represent two schemes for managing the PTE A/D >> bits. When the PTE A/D bits need to be set, Svade extension intdicates >> that a related page fault will be raised. In contrast, the Svadu >> extension >> supports hardware updating of PTE A/D bits. Since the Svade extension is >> mandatory and the Svadu extension is optional in RVA23 profile, by >> default >> the M-mode firmware will enable the Svadu extension in the menvcfg CSR >> when only Svadu is present in DT. >> >> This patch detects Svade and Svadu extensions from DT and adds >> arch_has_hw_pte_young() to enable optimization in MGLRU and >> __wp_page_copy_user() when we have the PTE A/D bits hardware updating >> support. >> >> Co-developed-by: Jinyu Tang >> Signed-off-by: Jinyu Tang >> Signed-off-by: Yong-Xuan Wang >> Reviewed-by: Andrew Jones >> --- >> ? arch/riscv/Kconfig?????????????? |? 1 + >> ? arch/riscv/include/asm/csr.h???? |? 1 + >> ? arch/riscv/include/asm/hwcap.h?? |? 2 ++ >> ? arch/riscv/include/asm/pgtable.h | 13 ++++++++++++- >> ? arch/riscv/kernel/cpufeature.c?? | 32 ++++++++++++++++++++++++++++++++ >> ? 5 files changed, 48 insertions(+), 1 deletion(-) >> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >> index 0525ee2d63c7..3d705e28ff85 100644 >> --- a/arch/riscv/Kconfig >> +++ b/arch/riscv/Kconfig >> @@ -36,6 +36,7 @@ config RISCV >> ????? select ARCH_HAS_PMEM_API >> ????? select ARCH_HAS_PREPARE_SYNC_CORE_CMD >> ????? select ARCH_HAS_PTE_SPECIAL >> +??? select ARCH_HAS_HW_PTE_YOUNG >> ????? select ARCH_HAS_SET_DIRECT_MAP if MMU >> ????? select ARCH_HAS_SET_MEMORY if MMU >> ????? select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL >> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h >> index 25966995da04..524cd4131c71 100644 >> --- a/arch/riscv/include/asm/csr.h >> +++ b/arch/riscv/include/asm/csr.h >> @@ -195,6 +195,7 @@ >> ? /* xENVCFG flags */ >> ? #define ENVCFG_STCE??????????? (_AC(1, ULL) << 63) >> ? #define ENVCFG_PBMTE??????????? (_AC(1, ULL) << 62) >> +#define ENVCFG_ADUE??????????? (_AC(1, ULL) << 61) >> ? #define ENVCFG_CBZE??????????? (_AC(1, UL) << 7) >> ? #define ENVCFG_CBCFE??????????? (_AC(1, UL) << 6) >> ? #define ENVCFG_CBIE_SHIFT??????? 4 >> diff --git a/arch/riscv/include/asm/hwcap.h >> b/arch/riscv/include/asm/hwcap.h >> index e17d0078a651..35d7aa49785d 100644 >> --- a/arch/riscv/include/asm/hwcap.h >> +++ b/arch/riscv/include/asm/hwcap.h >> @@ -81,6 +81,8 @@ >> ? #define RISCV_ISA_EXT_ZTSO??????? 72 >> ? #define RISCV_ISA_EXT_ZACAS??????? 73 >> ? #define RISCV_ISA_EXT_XANDESPMU??????? 74 >> +#define RISCV_ISA_EXT_SVADE???????????? 75 >> +#define RISCV_ISA_EXT_SVADU??????? 76 >> ? ? #define RISCV_ISA_EXT_XLINUXENVCFG??? 127 >> ? diff --git a/arch/riscv/include/asm/pgtable.h >> b/arch/riscv/include/asm/pgtable.h >> index aad8b8ca51f1..ec0cdacd7da0 100644 >> --- a/arch/riscv/include/asm/pgtable.h >> +++ b/arch/riscv/include/asm/pgtable.h >> @@ -120,6 +120,7 @@ >> ? #include >> ? #include >> ? #include >> +#include >> ? ? #define __page_val_to_pfn(_val)? (((_val) & _PAGE_PFN_MASK) >> >> _PAGE_PFN_SHIFT) >> ? @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud) >> ? } >> ? ? #ifdef CONFIG_RISCV_ISA_SVNAPOT >> -#include >> ? ? static __always_inline bool has_svnapot(void) >> ? { >> @@ -624,6 +624,17 @@ static inline pgprot_t >> pgprot_writecombine(pgprot_t _prot) >> ????? return __pgprot(prot); >> ? } >> ? +/* >> + * Both Svade and Svadu control the hardware behavior when the PTE >> A/D bits need to be set. By >> + * default the M-mode firmware enables the hardware updating scheme >> when only Svadu is present in >> + * DT. >> + */ >> +#define arch_has_hw_pte_young arch_has_hw_pte_young >> +static inline bool arch_has_hw_pte_young(void) >> +{ >> +??? return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); >> +} >> + >> ? /* >> ?? * THP functions >> ?? */ >> diff --git a/arch/riscv/kernel/cpufeature.c >> b/arch/riscv/kernel/cpufeature.c >> index 5ef48cb20ee1..b2c3fe945e89 100644 >> --- a/arch/riscv/kernel/cpufeature.c >> +++ b/arch/riscv/kernel/cpufeature.c >> @@ -301,6 +301,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { >> ????? __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), >> ????? __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), >> ????? __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), >> +??? __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), >> +??? __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), >> ????? __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), >> ????? __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), >> ????? __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), >> @@ -554,6 +556,21 @@ static void __init >> riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) >> ????????????? clear_bit(RISCV_ISA_EXT_v, isainfo->isa); >> ????????? } >> ? +??????? /* >> +???????? * When neither Svade nor Svadu present in DT, it is technically >> +???????? * unknown whether the platform uses Svade or Svadu. >> Supervisor may >> +???????? * assume Svade to be present and enabled or it can discover >> based >> +???????? * on mvendorid, marchid, and mimpid. When both Svade and >> Svadu present >> +???????? * in DT, supervisor must assume Svadu turned-off at boot >> time. To use >> +???????? * Svadu, supervisor must explicitly enable it using the SBI >> FWFT extension. >> +???????? */ >> +??????? if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && >> +??????????? !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) >> +??????????? set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa); >> +??????? else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && >> +???????????? test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) >> +??????????? clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa); >> + >> ????????? /* >> ?????????? * All "okay" hart should have same isa. Set HWCAP based on >> ?????????? * common capabilities of every "okay" hart, in case they don't >> @@ -619,6 +636,21 @@ static int __init >> riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) >> ? ????????? of_node_put(cpu_node); >> ? +??????? /* >> +???????? * When neither Svade nor Svadu present in DT, it is technically >> +???????? * unknown whether the platform uses Svade or Svadu. >> Supervisor may >> +???????? * assume Svade to be present and enabled or it can discover >> based >> +???????? * on mvendorid, marchid, and mimpid. When both Svade and >> Svadu present >> +???????? * in DT, supervisor must assume Svadu turned-off at boot >> time. To use >> +???????? * Svadu, supervisor must explicitly enable it using the SBI >> FWFT extension. >> +???????? */ >> +??????? if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && >> +??????????? !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) >> +??????????? set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa); >> +??????? else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && >> +???????????? test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) >> +??????????? clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa); >> + This is a duplicate of the previous chunk of code. Moreover, now that we have a .validate callback for ISA extension (in for-next), I would prefer this to be based on that support rather that having duplicated extension specific handling code. I think this could be translated (almost) using the following .validate() callback for SVADU/SVADE extension: static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { /* SVADE has already been detected, use SVADE only */ if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE)) return -ENOTSUPP; return 0; } static int riscv_ext_svade_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { /* Clear SVADU, it will be enable using the FWFT extension if present */ clear_bit(RISCV_ISA_EXT_SVADU, isa_bitmap); return 0; } However, this will not enable SVADE if neither SVADU/SVADE are set (as done by your patch) but since SVADE does not seems to be used explicitly in your patch series, I think it is sane to keep it like that. Thanks, Cl?ment >> ????????? /* >> ?????????? * All "okay" harts should have same isa. Set HWCAP based on >> ?????????? * common capabilities of every "okay" hart, in case they >> don't. > > > Reviewed-by: Alexandre Ghiti > > Thanks, > > Alex > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3417BC3DA59 for ; Fri, 19 Jul 2024 07:38:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JzR+PQZHPg4qPgMfkXkLp3AdVmJqEpNIBeNf8NZim7c=; b=XxIKfkbH5XPpeU 2HDBMIPSpLOEiba9aqW6yItiVy6jeWm+xZ3VreZrb8cKfaZ0+Ot0YLuV58Ko9gGIcgnD/69YemiQO se9b34X8qphHbl5OmqvzDm7HJuUWKYIrH4BczVl5NKB8kUbqTyaMHDfg60JXoxNbYK/9VwKgUZLse 6gx+ukqItaY/s4xmQJfX8Bi3vzqc2f+rQDvEQGdgz6IEP3jejb/CraTLjijg6AvPGatktV9Sy/Oug Uv3t0uXUGiGvXR4CiQHAzKptF51zAW6Qv/24SaEyyjjEQG2WoA9TY9xAwFM0QcV7QKG4sQyDbX/JQ MmAndpBkHjP8aU+6tMmw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sUiBw-00000001w86-3CEi; Fri, 19 Jul 2024 07:38:12 +0000 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sUiBs-00000001w69-2noW for linux-riscv@lists.infradead.org; Fri, 19 Jul 2024 07:38:10 +0000 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-42671c659e4so973965e9.3 for ; Fri, 19 Jul 2024 00:38:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721374687; x=1721979487; darn=lists.infradead.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=jwgXEqFoIQ8Qnw3vnSPZZVOe2UVdpjRinxoXuv0AT+s=; b=wQFCMTWXFHLyKIk16nmmtxJ9mED64EKILcDXTqfmsX00RbgGF6+efoJJJSS0bMnda8 VK6bqUtz25EiQKkL+jaFn56I6Hdu+e2bafzmtpaMjNDpw2urUccAap7uDVhTw1tGK0KP EHR0GN1umWalQk/Xs8TlaFPyzGDBaILAQHREA3k9rurCvelR9liXpaic78yob0QLaLt9 oQzz32lYGKuZzqgCoapdl/pm6f0gaIVPE7M3pHz3TgCuUNXHqBzhch597RTtVAIe2xgn bqsVqRTIt5/Ls52UtS98Pg8U9EXHJVFI+v/ARxHCXL+GlIlJ7AowkQO6BabAuPWkEzQ6 wvzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721374687; x=1721979487; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=jwgXEqFoIQ8Qnw3vnSPZZVOe2UVdpjRinxoXuv0AT+s=; b=OmIQWngcfwYq7dS0+l8K3atXgmg/uFzZv7TgVlOE1+VOrXczvGrGQWjdUAdePjlrvS fLOSGpcAYp+uwmSz0f5cov8E5Gs4Ww0z5JHED16dz7r4Xtu31DbGoMowBore0BzIrQYp VM2zmLwsCERFzpwGgemx3me0kasbuk2ZuWYABBGT/a53xO4y2rBs4EyRrOB5uRewe2PH 0/0aRqWHh8IcuRFSN0Xd5FviLtEZP06BuQrQBsUM+FA/p9lnzF7NenxLVM0tmXCF6sCP R4eHabeOpUu4lkKyHnINImOnvwYIdK8tYFfm8XhtE9Tuos9zlDNRSUoQ3Ayv5Hhyj3nr GHPg== X-Forwarded-Encrypted: i=1; AJvYcCWTwfDTS9lvOmvY6X5j9DJ3MmZcnK5U2lmbhVD9wF2HkvsccoOVay0TVctvFnhEXgKNGoRsNoZgPBqgxg==@lists.infradead.org X-Gm-Message-State: AOJu0YzjMrjHh+LQeQB+on07RwuJsPUY2ITjGOFcNwpnsob+shEo0alR AqFo7jfj+q+nJewvz9XvT0865fMLiy+tszYXRoWSEtHO/YpKQi+JVKRt/RJOxEo= X-Google-Smtp-Source: AGHT+IEZptXdeMHbUpkxHv4M1h0uA22gKqUctjYLtu3zi6c+9V9bfZiObnfgruMuoet83T2afxZhsg== X-Received: by 2002:a05:600c:3c9f:b0:425:7ac6:96f9 with SMTP id 5b1f17b1804b1-427d5b80f8fmr5754795e9.0.1721374686645; Fri, 19 Jul 2024 00:38:06 -0700 (PDT) Received: from ?IPV6:2a01:e0a:e17:9700:16d2:7456:6634:9626? ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d6906c77sm14275665e9.23.2024.07.19.00.38.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jul 2024 00:38:06 -0700 (PDT) Message-ID: <2f1c7dff-168e-4ad0-b426-cfe99fc33fd0@rivosinc.com> Date: Fri, 19 Jul 2024 09:38:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 1/4] RISC-V: Add Svade and Svadu Extensions Support To: Alexandre Ghiti , Yong-Xuan Wang , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Jinyu Tang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , Anup Patel , Conor Dooley , Mayuresh Chitale , Atish Patra , Samuel Ortiz , Daniel Henrique Barboza , Samuel Holland , Evan Green , Xiao Wang , Alexandre Ghiti , Andrew Morton , Kemeng Shi , "Mike Rapoport (IBM)" , Leonardo Bras , Charlie Jenkins , "Matthew Wilcox (Oracle)" , Jisheng Zhang References: <20240712083850.4242-1-yongxuan.wang@sifive.com> <20240712083850.4242-2-yongxuan.wang@sifive.com> <6ad0c386-6777-4467-bab4-8fba149f3bfe@ghiti.fr> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: <6ad0c386-6777-4467-bab4-8fba149f3bfe@ghiti.fr> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240719_003808_748399_8E41BE05 X-CRM114-Status: GOOD ( 26.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org CgpIaSBZb25nLVh1YW4sCgoKT24gMTgvMDcvMjAyNCAxODo0MywgQWxleGFuZHJlIEdoaXRpIHdy b3RlOgo+IEhpIFlvbmctWHVhbiwKPiAKPiBPbiAxMi8wNy8yMDI0IDEwOjM4LCBZb25nLVh1YW4g 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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d6906c77sm14275665e9.23.2024.07.19.00.38.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jul 2024 00:38:06 -0700 (PDT) Message-ID: <2f1c7dff-168e-4ad0-b426-cfe99fc33fd0@rivosinc.com> Date: Fri, 19 Jul 2024 09:38:04 +0200 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 1/4] RISC-V: Add Svade and Svadu Extensions Support To: Alexandre Ghiti , Yong-Xuan Wang , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Jinyu Tang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , Anup Patel , Conor Dooley , Mayuresh Chitale , Atish Patra , Samuel Ortiz , Daniel Henrique Barboza , Samuel Holland , Evan Green , Xiao Wang , Alexandre Ghiti , Andrew Morton , Kemeng Shi , "Mike Rapoport (IBM)" , Leonardo Bras , Charlie Jenkins , "Matthew Wilcox (Oracle)" , Jisheng Zhang References: <20240712083850.4242-1-yongxuan.wang@sifive.com> <20240712083850.4242-2-yongxuan.wang@sifive.com> <6ad0c386-6777-4467-bab4-8fba149f3bfe@ghiti.fr> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: <6ad0c386-6777-4467-bab4-8fba149f3bfe@ghiti.fr> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Yong-Xuan, On 18/07/2024 18:43, Alexandre Ghiti wrote: > Hi Yong-Xuan, > > On 12/07/2024 10:38, Yong-Xuan Wang wrote: >> Svade and Svadu extensions represent two schemes for managing the PTE A/D >> bits. When the PTE A/D bits need to be set, Svade extension intdicates >> that a related page fault will be raised. In contrast, the Svadu >> extension >> supports hardware updating of PTE A/D bits. Since the Svade extension is >> mandatory and the Svadu extension is optional in RVA23 profile, by >> default >> the M-mode firmware will enable the Svadu extension in the menvcfg CSR >> when only Svadu is present in DT. >> >> This patch detects Svade and Svadu extensions from DT and adds >> arch_has_hw_pte_young() to enable optimization in MGLRU and >> __wp_page_copy_user() when we have the PTE A/D bits hardware updating >> support. >> >> Co-developed-by: Jinyu Tang >> Signed-off-by: Jinyu Tang >> Signed-off-by: Yong-Xuan Wang >> Reviewed-by: Andrew Jones >> --- >>   arch/riscv/Kconfig               |  1 + >>   arch/riscv/include/asm/csr.h     |  1 + >>   arch/riscv/include/asm/hwcap.h   |  2 ++ >>   arch/riscv/include/asm/pgtable.h | 13 ++++++++++++- >>   arch/riscv/kernel/cpufeature.c   | 32 ++++++++++++++++++++++++++++++++ >>   5 files changed, 48 insertions(+), 1 deletion(-) >> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >> index 0525ee2d63c7..3d705e28ff85 100644 >> --- a/arch/riscv/Kconfig >> +++ b/arch/riscv/Kconfig >> @@ -36,6 +36,7 @@ config RISCV >>       select ARCH_HAS_PMEM_API >>       select ARCH_HAS_PREPARE_SYNC_CORE_CMD >>       select ARCH_HAS_PTE_SPECIAL >> +    select ARCH_HAS_HW_PTE_YOUNG >>       select ARCH_HAS_SET_DIRECT_MAP if MMU >>       select ARCH_HAS_SET_MEMORY if MMU >>       select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL >> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h >> index 25966995da04..524cd4131c71 100644 >> --- a/arch/riscv/include/asm/csr.h >> +++ b/arch/riscv/include/asm/csr.h >> @@ -195,6 +195,7 @@ >>   /* xENVCFG flags */ >>   #define ENVCFG_STCE            (_AC(1, ULL) << 63) >>   #define ENVCFG_PBMTE            (_AC(1, ULL) << 62) >> +#define ENVCFG_ADUE            (_AC(1, ULL) << 61) >>   #define ENVCFG_CBZE            (_AC(1, UL) << 7) >>   #define ENVCFG_CBCFE            (_AC(1, UL) << 6) >>   #define ENVCFG_CBIE_SHIFT        4 >> diff --git a/arch/riscv/include/asm/hwcap.h >> b/arch/riscv/include/asm/hwcap.h >> index e17d0078a651..35d7aa49785d 100644 >> --- a/arch/riscv/include/asm/hwcap.h >> +++ b/arch/riscv/include/asm/hwcap.h >> @@ -81,6 +81,8 @@ >>   #define RISCV_ISA_EXT_ZTSO        72 >>   #define RISCV_ISA_EXT_ZACAS        73 >>   #define RISCV_ISA_EXT_XANDESPMU        74 >> +#define RISCV_ISA_EXT_SVADE             75 >> +#define RISCV_ISA_EXT_SVADU        76 >>     #define RISCV_ISA_EXT_XLINUXENVCFG    127 >>   diff --git a/arch/riscv/include/asm/pgtable.h >> b/arch/riscv/include/asm/pgtable.h >> index aad8b8ca51f1..ec0cdacd7da0 100644 >> --- a/arch/riscv/include/asm/pgtable.h >> +++ b/arch/riscv/include/asm/pgtable.h >> @@ -120,6 +120,7 @@ >>   #include >>   #include >>   #include >> +#include >>     #define __page_val_to_pfn(_val)  (((_val) & _PAGE_PFN_MASK) >> >> _PAGE_PFN_SHIFT) >>   @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud) >>   } >>     #ifdef CONFIG_RISCV_ISA_SVNAPOT >> -#include >>     static __always_inline bool has_svnapot(void) >>   { >> @@ -624,6 +624,17 @@ static inline pgprot_t >> pgprot_writecombine(pgprot_t _prot) >>       return __pgprot(prot); >>   } >>   +/* >> + * Both Svade and Svadu control the hardware behavior when the PTE >> A/D bits need to be set. By >> + * default the M-mode firmware enables the hardware updating scheme >> when only Svadu is present in >> + * DT. >> + */ >> +#define arch_has_hw_pte_young arch_has_hw_pte_young >> +static inline bool arch_has_hw_pte_young(void) >> +{ >> +    return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); >> +} >> + >>   /* >>    * THP functions >>    */ >> diff --git a/arch/riscv/kernel/cpufeature.c >> b/arch/riscv/kernel/cpufeature.c >> index 5ef48cb20ee1..b2c3fe945e89 100644 >> --- a/arch/riscv/kernel/cpufeature.c >> +++ b/arch/riscv/kernel/cpufeature.c >> @@ -301,6 +301,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { >>       __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), >>       __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), >>       __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), >> +    __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), >> +    __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), >>       __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), >>       __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), >>       __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), >> @@ -554,6 +556,21 @@ static void __init >> riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) >>               clear_bit(RISCV_ISA_EXT_v, isainfo->isa); >>           } >>   +        /* >> +         * When neither Svade nor Svadu present in DT, it is technically >> +         * unknown whether the platform uses Svade or Svadu. >> Supervisor may >> +         * assume Svade to be present and enabled or it can discover >> based >> +         * on mvendorid, marchid, and mimpid. When both Svade and >> Svadu present >> +         * in DT, supervisor must assume Svadu turned-off at boot >> time. To use >> +         * Svadu, supervisor must explicitly enable it using the SBI >> FWFT extension. >> +         */ >> +        if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && >> +            !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) >> +            set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa); >> +        else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && >> +             test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) >> +            clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa); >> + >>           /* >>            * All "okay" hart should have same isa. Set HWCAP based on >>            * common capabilities of every "okay" hart, in case they don't >> @@ -619,6 +636,21 @@ static int __init >> riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) >>             of_node_put(cpu_node); >>   +        /* >> +         * When neither Svade nor Svadu present in DT, it is technically >> +         * unknown whether the platform uses Svade or Svadu. >> Supervisor may >> +         * assume Svade to be present and enabled or it can discover >> based >> +         * on mvendorid, marchid, and mimpid. When both Svade and >> Svadu present >> +         * in DT, supervisor must assume Svadu turned-off at boot >> time. To use >> +         * Svadu, supervisor must explicitly enable it using the SBI >> FWFT extension. >> +         */ >> +        if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && >> +            !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) >> +            set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa); >> +        else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && >> +             test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) >> +            clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa); >> + This is a duplicate of the previous chunk of code. Moreover, now that we have a .validate callback for ISA extension (in for-next), I would prefer this to be based on that support rather that having duplicated extension specific handling code. I think this could be translated (almost) using the following .validate() callback for SVADU/SVADE extension: static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { /* SVADE has already been detected, use SVADE only */ if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE)) return -ENOTSUPP; return 0; } static int riscv_ext_svade_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { /* Clear SVADU, it will be enable using the FWFT extension if present */ clear_bit(RISCV_ISA_EXT_SVADU, isa_bitmap); return 0; } However, this will not enable SVADE if neither SVADU/SVADE are set (as done by your patch) but since SVADE does not seems to be used explicitly in your patch series, I think it is sane to keep it like that. Thanks, Clément >>           /* >>            * All "okay" harts should have same isa. Set HWCAP based on >>            * common capabilities of every "okay" hart, in case they >> don't. > > > Reviewed-by: Alexandre Ghiti > > Thanks, > > Alex >