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Tue, 31 Mar 2020 02:39:42 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id B0642C433BA; Tue, 31 Mar 2020 02:39:42 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: tingwei) by smtp.codeaurora.org (Postfix) with ESMTPSA id 36F9BC433D2; Tue, 31 Mar 2020 02:39:42 +0000 (UTC) MIME-Version: 1.0 Date: Tue, 31 Mar 2020 10:39:42 +0800 From: tingwei@codeaurora.org To: Will Deacon Subject: Re: [PATCH] arm64: hw_breakpoint: don't clear debug registers in halt mode In-Reply-To: <20200330134218.GB10633@willie-the-truck> References: <20200328083209.21793-1-tingwei@codeaurora.org> <20200330123946.GH1309@C02TD0UTHF1T.local> <20200330134218.GB10633@willie-the-truck> Message-ID: <2f4d076b2b21de3908f0821126d0c61e@codeaurora.org> X-Sender: tingwei@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200330_193956_541000_A0C227B8 X-CRM114-Status: GOOD ( 18.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org 5ZyoIDIwMjAtMDMtMzAgMjE6NDLvvIxXaWxsIERlYWNvbiDlhpnpgZPvvJoKPiBPbiBNb24sIE1h ciAzMCwgMjAyMCBhdCAwMTozOTo0NlBNICswMTAwLCBNYXJrIFJ1dGxhbmQgd3JvdGU6Cj4+IE9u IFNhdCwgTWFyIDI4LCAyMDIwIGF0IDA0OjMyOjA5UE0gKzA4MDAsIFRpbmd3ZWkgWmhhbmcgd3Jv dGU6Cj4+ID4gSWYgZXh0ZXJuYWwgZGVidWdnZXIgc2V0cyBhIGJyZWFrcG9pbnQgZm9yIG9uZSBL ZXJuZWwgZnVuY3Rpb24KPj4gPiB3aGVuIGRldmljZSBpcyBpbiBib290bG9hZGVyIG1vZGUgYW5k IGxvYWRzIEtlcm5lbCwgdGhpcyBicmVha3BvaW50Cj4+ID4gd2lsbCBiZSB3aXBlZCBvdXQgaW4g aHdfYnJlYWtwb2ludF9yZXNldCgpLiBUbyBmaXggdGhpcywgY2hlY2sKPj4gPiBNRFNDUl9FTDEu SERFIGluIGh3X2JyZWFrcG9pbnRfcmVzZXQoKS4gV2hlbiBNRFNDUl9FTDEuSERFIGlzCj4+ID4g MGIxLCBoYWx0aW5nIGRlYnVnIGlzIGVuYWJsZWQuIERvbid0IHJlc2V0IGRlYnVnIHJlZ2lzdGVy cyBpbiB0aGlzCj4gY2FzZS4KPj4gCj4+IEkgZG9uJ3QgdGhpbmsgdGhpcyBpcyBzdWZmaWNpZW50 LCBiZWNhdXNlIHRoZSBrZXJuZWwgY2FuIHN0aWxsCj4+IHN1YnNlcXVlbnRseSBtZXNzIHdpdGgg YnJlYWtwb2ludHMsIGFuZCB0aGUgSFcgZGVidWdnZXIgbWlnaHQgbm90IGJlCj4+IGF0dGFjaGVk IGF0IHRoaXMgcG9pbnQgaW4gdGltZSBhbnlob3cuCj4+IAo+PiBJIHJlY2tvbiB0aGlzIHNob3Vs ZCBoYW5nIG9mZiB0aGUgZXhpc3RpbmcgIm5vZGVidW1vbiIgY29tbWFuZCBsaW5lCj4+IG9wdGlv biwgYW5kIHdlIHNob3VsZG4ndCB1c2UgSFcgYnJlYWtwb2ludHMgYXQgYWxsIHdoZW4gdGhhdCBp cyAKPj4gcGFzc2VkLgo+PiBUaGVuIHlvdSBjYW4gcGFzcyB0aGF0IHRvIHByZXZlbnQgdGhlIGtl cm5lbCBzdG9tcGluZyBvbiB0aGUgZXh0ZXJuYWwKPj4gZGVidWdnZXIuCj4+IAo+PiBXaWxsLCB0 aG91Z2h0cz8KPiAKPiBJIHdhcyBnb2luZyB0byBzdWdnZXN0IHRoZSBzYW1lIHRoaW5nLCBhbHRo b3VnaCB3ZSB3aWxsIGFsc28gbmVlZCB0byAKPiB0YWtlCj4gY2FyZSB0byByZXNldCB0aGUgcmVn aXN0ZXJzIGlmICJub2RlYnVnbW9uIiBpcyB0b2dnbGVkIGF0IHJ1bnRpbWUgdmlhIAo+IHRoZQo+ ICJkZWJ1Z19lbmFibGVkIiBmaWxlIGluIGRlYnVnZnMuCj4gCj4gV2lsbAoKVGhhbmtzIGZvciB0 aGUgc3VnZ2VzdGlvbiwgTWFyayBhbmQgV2lsbC4gSXQncyBhIGdyZWF0IGlkZWEgdG8gdXNlCiJu b2RlYnVnbW9uIi4gV2hlbiAibm9kZWJ1Z21vbiIgaXMgc2V0LCBLZXJuZWwgd29uJ3QgY2hhbmdl IEhXIApicmVha3BvaW50cy4KCkZvciByZXNldCB0aGUgcmVnaXN0ZXJzIGFmdGVyICJkZWJ1Z19l bmFibGVkIiBpcyB0b2dnbGVkLCBJJ20gdGhpbmtpbmcgCmlmCndlIGFyZSBhZGRpbmcgdW5uZWNl c3NhcnkgY29tcGxleGl0eSBoZXJlLklmIHdlIHRha2UgdGhhdCBhcHByb2FjaCwgd2UgCndpbGwK aG9vayAiZGVidWdfZW5hYmxlZCIgaW50ZXJmYWNlIGFuZCB1c2Ugc21wX2NhbGxfZnVuY3Rpb25f c2luZ2xlKCkgdG8gCmNhbGwKaHdfYnJlYWtwb2ludF9yZXNldCgpIG9uIGVhY2ggQ1BVLiBXYWl0 IGZvciBhbGwgQ1BVcycgZXhlY3V0aW9uIGRvbmUgYW5kCmNoYW5nZSAiZGVidWdfZW5hYmxlZCIu IEV4dGVybmFsIGRlYnVnZ2VyIHdvdWxkIGNsZWFyIHRoZSBicmVha3BvaW50cyAKd2hlbgppdCBk ZXRhY2hlcyB0aGUgZGV2aWNlIGFuZCByZXN0b3JlcyBpdHMgYnJlYWtwb2ludHMgd2hlbiBhdHRh Y2hlcyB0aGUgCmRldmljZS4KQXNzdW1lIGRlYnVnX2VuYWJsZWQgaXMgY2hhbmdlZCB0byBvbmUg YWZ0ZXIgZXh0ZXJuYWwgZGVidWdnZXIgZGV0YWNoZXMgCnRoZQpkZXZpY2UuIERlYnVnZ2VyIHdv dWxkIGFscmVhZHkgY2xlYXIgdGhlIGJyZWFrcG9pbnQgcmVnaXN0ZXJzLiBJZiAKZGViZ2dlciBp cwpzdGlsbCBhdHRhY2hlZCwgdGhlcmUncyBub3RoaW5nIEtlcm5lbCBjYW4gZG8gdG8gc3RvcCBp dCAKcmVzdG9yZXMvcHJvZ3JhbXMKdGhlIGJyZWFrcG9pbnQgcmVnaXN0ZXJzLgoKV2hhdCBkbyB5 b3UgdGhpbmsgb2YgdGhpcz8KClRoYW5rcywKVGluZ3dlaQoKX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QK bGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRl YWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1FD4C43331 for ; Tue, 31 Mar 2020 02:39:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 844FB20748 for ; Tue, 31 Mar 2020 02:39:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="u7OnbxbR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729464AbgCaCjs (ORCPT ); Mon, 30 Mar 2020 22:39:48 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:16767 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727464AbgCaCjs (ORCPT ); Mon, 30 Mar 2020 22:39:48 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1585622388; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=F0cnuHPPoBwL4ZXyaNpltI2ZJBgY3zhLpDoVyFkzMWU=; b=u7OnbxbRA4BS1CZ5WFRSnJ1FKlw41x2Te+q+9fN99lDJmN4EokmAFec8FG7RIV5xb0CIGxmQ QSKpNhKbxWuRVz8ef5fYlNSUq5HTYhHKk2TYxy+Pw9YE3AfU0cR+ns0Keqf0dLawN1NJeJUT gH9NdbNsXjxBDOfE6ayq/C9kM/8= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e82ad6e.7f8e52e5be68-smtp-out-n03; Tue, 31 Mar 2020 02:39:42 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 864B1C433F2; Tue, 31 Mar 2020 02:39:42 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: tingwei) by smtp.codeaurora.org (Postfix) with ESMTPSA id 36F9BC433D2; Tue, 31 Mar 2020 02:39:42 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Date: Tue, 31 Mar 2020 10:39:42 +0800 From: tingwei@codeaurora.org To: Will Deacon Cc: Mark Rutland , Catalin Marinas , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: hw_breakpoint: don't clear debug registers in halt mode In-Reply-To: <20200330134218.GB10633@willie-the-truck> References: <20200328083209.21793-1-tingwei@codeaurora.org> <20200330123946.GH1309@C02TD0UTHF1T.local> <20200330134218.GB10633@willie-the-truck> Message-ID: <2f4d076b2b21de3908f0821126d0c61e@codeaurora.org> X-Sender: tingwei@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2020-03-30 21:42，Will Deacon 写道： > On Mon, Mar 30, 2020 at 01:39:46PM +0100, Mark Rutland wrote: >> On Sat, Mar 28, 2020 at 04:32:09PM +0800, Tingwei Zhang wrote: >> > If external debugger sets a breakpoint for one Kernel function >> > when device is in bootloader mode and loads Kernel, this breakpoint >> > will be wiped out in hw_breakpoint_reset(). To fix this, check >> > MDSCR_EL1.HDE in hw_breakpoint_reset(). When MDSCR_EL1.HDE is >> > 0b1, halting debug is enabled. Don't reset debug registers in this > case. >> >> I don't think this is sufficient, because the kernel can still >> subsequently mess with breakpoints, and the HW debugger might not be >> attached at this point in time anyhow. >> >> I reckon this should hang off the existing "nodebumon" command line >> option, and we shouldn't use HW breakpoints at all when that is >> passed. >> Then you can pass that to prevent the kernel stomping on the external >> debugger. >> >> Will, thoughts? > > I was going to suggest the same thing, although we will also need to > take > care to reset the registers if "nodebugmon" is toggled at runtime via > the > "debug_enabled" file in debugfs. > > Will Thanks for the suggestion, Mark and Will. It's a great idea to use "nodebugmon". When "nodebugmon" is set, Kernel won't change HW breakpoints. For reset the registers after "debug_enabled" is toggled, I'm thinking if we are adding unnecessary complexity here.If we take that approach, we will hook "debug_enabled" interface and use smp_call_function_single() to call hw_breakpoint_reset() on each CPU. Wait for all CPUs' execution done and change "debug_enabled". External debugger would clear the breakpoints when it detaches the device and restores its breakpoints when attaches the device. Assume debug_enabled is changed to one after external debugger detaches the device. Debugger would already clear the breakpoint registers. If debgger is still attached, there's nothing Kernel can do to stop it restores/programs the breakpoint registers. What do you think of this? Thanks, Tingwei