From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com
Subject: Re: [PATCH v6 09/14] tcg/riscv: Accept constant first argument to sub_vec
Date: Tue, 22 Oct 2024 14:31:59 +0800 [thread overview]
Message-ID: <2fb117f7-55ca-4b07-838e-3ba629605e2b@linux.alibaba.com> (raw)
In-Reply-To: <20241016193140.2206352-10-richard.henderson@linaro.org>
On 2024/10/17 03:31, Richard Henderson wrote:
> Use vrsub.vi to subtract from a constant.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/riscv/tcg-target-con-set.h | 1 +
> tcg/riscv/tcg-target.c.inc | 8 ++++++--
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
> index 97e6ecdb0f..d8ce5414f5 100644
> --- a/tcg/riscv/tcg-target-con-set.h
> +++ b/tcg/riscv/tcg-target-con-set.h
> @@ -25,6 +25,7 @@ C_O0_I2(v, r)
> C_O1_I1(v, r)
> C_O1_I1(v, v)
> C_O1_I2(v, v, v)
> +C_O1_I2(v, vK, v)
> C_O1_I2(v, v, vK)
> C_O1_I2(v, v, vL)
> C_O1_I4(v, v, vL, vK, vK)
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index ce8d6d0293..1ce2f291d3 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -2350,7 +2350,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
> break;
> case INDEX_op_sub_vec:
> set_vtype_len_sew(s, type, vece);
> - tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2);
> + if (const_args[1]) {
> + tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a2, a1);
> + } else {
> + tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2);
> + }
> break;
> case INDEX_op_and_vec:
> set_vtype_len(s, type);
> @@ -2565,7 +2569,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
> case INDEX_op_xor_vec:
> return C_O1_I2(v, v, vK);
> case INDEX_op_sub_vec:
> - return C_O1_I2(v, v, v);
> + return C_O1_I2(v, vK, v);
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> case INDEX_op_cmp_vec:
> return C_O1_I2(v, v, vL);
> case INDEX_op_cmpsel_vec:
next prev parent reply other threads:[~2024-10-22 6:32 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-16 19:31 [PATCH v6 00/14] tcg/riscv: Add support for vector Richard Henderson
2024-10-16 19:31 ` [PATCH v6 01/14] tcg: Reset data_gen_ptr correctly Richard Henderson
2024-10-21 1:16 ` Alistair Francis
2024-10-21 17:31 ` Pierrick Bouvier
2024-10-22 2:48 ` LIU Zhiwei
2024-10-16 19:31 ` [PATCH v6 02/14] disas/riscv: Fix vsetivli disassembly Richard Henderson
2024-10-21 1:17 ` Alistair Francis
2024-10-21 17:41 ` Pierrick Bouvier
2024-10-22 3:12 ` LIU Zhiwei
2024-10-16 19:31 ` [PATCH v6 03/14] util: Add RISC-V vector extension probe in cpuinfo Richard Henderson
2024-10-21 1:20 ` Alistair Francis
2024-10-21 18:25 ` Daniel Henrique Barboza
2024-10-21 18:52 ` Richard Henderson
2024-10-21 19:16 ` Daniel Henrique Barboza
2024-10-16 19:31 ` [PATCH v6 04/14] tcg/riscv: Add basic support for vector Richard Henderson
2024-10-16 19:31 ` [PATCH v6 05/14] tcg/riscv: Implement vector mov/dup{m/i} Richard Henderson
2024-10-16 19:31 ` [PATCH v6 06/14] tcg/riscv: Add support for basic vector opcodes Richard Henderson
2024-10-16 19:31 ` [PATCH v6 07/14] tcg/riscv: Implement vector cmp/cmpsel ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 08/14] tcg/riscv: Implement vector neg ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 09/14] tcg/riscv: Accept constant first argument to sub_vec Richard Henderson
2024-10-22 6:31 ` LIU Zhiwei [this message]
2024-10-16 19:31 ` [PATCH v6 10/14] tcg/riscv: Implement vector sat/mul ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 11/14] tcg/riscv: Implement vector min/max ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 12/14] tcg/riscv: Implement vector shi/s/v ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 13/14] tcg/riscv: Implement vector roti/v/x ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 14/14] tcg/riscv: Enable native vector support for TCG host Richard Henderson
2024-10-21 1:42 ` [PATCH v6 00/14] tcg/riscv: Add support for vector Alistair Francis
2024-10-22 6:59 ` LIU Zhiwei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2fb117f7-55ca-4b07-838e-3ba629605e2b@linux.alibaba.com \
--to=zhiwei_liu@linux.alibaba.com \
--cc=alistair.francis@wdc.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.