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From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: "Sean Christopherson" <seanjc@google.com>,
	"Andrew Jones" <andrew.jones@linux.dev>,
	"Janosch Frank" <frankja@linux.ibm.com>,
	"Claudio Imbrenda" <imbrenda@linux.ibm.com>,
	"Nico Böhr" <nrb@linux.ibm.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>
Cc: kvm-riscv@lists.infradead.org, linux-s390@vger.kernel.org,
	kvm@vger.kernel.org
Subject: Re: [kvm-unit-tests PATCH 08/16] x86/pmu: Rename gp_counter_mask_length to arch_event_mask_length
Date: Tue, 10 Jun 2025 15:22:38 +0800	[thread overview]
Message-ID: <303a9aaa-eb52-47b2-af05-32df320dc52b@linux.intel.com> (raw)
In-Reply-To: <20250529221929.3807680-9-seanjc@google.com>


On 5/30/2025 6:19 AM, Sean Christopherson wrote:
> Rename gp_counter_mask_length to arch_event_mask_length to reflect what
> the field actually tracks.  The availablity of architectural events has
> nothing to do with the GP counters themselves.
>
> No functional change intended.
>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
>  lib/x86/pmu.c | 4 ++--
>  lib/x86/pmu.h | 2 +-
>  x86/pmu.c     | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c
> index 599168ac..b97e2c4a 100644
> --- a/lib/x86/pmu.c
> +++ b/lib/x86/pmu.c
> @@ -18,7 +18,7 @@ void pmu_init(void)
>  
>  		pmu.nr_gp_counters = (cpuid_10.a >> 8) & 0xff;
>  		pmu.gp_counter_width = (cpuid_10.a >> 16) & 0xff;
> -		pmu.gp_counter_mask_length = (cpuid_10.a >> 24) & 0xff;
> +		pmu.arch_event_mask_length = (cpuid_10.a >> 24) & 0xff;
>  
>  		/* CPUID.0xA.EBX bit is '1' if a counter is NOT available. */
>  		pmu.arch_event_available = ~cpuid_10.b;

Better to change to "pmu.arch_event_available = ~cpuid_10.b &
(BIT(pmu.arch_event_mask_length) - 1)" to follow SDM. Some newly introduced
architectural events like topdown metrics events doesn't exist on older
platforms.


> @@ -50,7 +50,7 @@ void pmu_init(void)
>  			pmu.msr_gp_event_select_base = MSR_K7_EVNTSEL0;
>  		}
>  		pmu.gp_counter_width = PMC_DEFAULT_WIDTH;
> -		pmu.gp_counter_mask_length = pmu.nr_gp_counters;
> +		pmu.arch_event_mask_length = pmu.nr_gp_counters;
>  		pmu.arch_event_available = (1u << pmu.nr_gp_counters) - 1;
>  
>  		if (this_cpu_has_perf_global_status()) {
> diff --git a/lib/x86/pmu.h b/lib/x86/pmu.h
> index d0ad280a..c7dc68c1 100644
> --- a/lib/x86/pmu.h
> +++ b/lib/x86/pmu.h
> @@ -63,7 +63,7 @@ struct pmu_caps {
>  	u8 fixed_counter_width;
>  	u8 nr_gp_counters;
>  	u8 gp_counter_width;
> -	u8 gp_counter_mask_length;
> +	u8 arch_event_mask_length;
>  	u32 arch_event_available;
>  	u32 msr_gp_counter_base;
>  	u32 msr_gp_event_select_base;
> diff --git a/x86/pmu.c b/x86/pmu.c
> index 0ce34433..63eae3db 100644
> --- a/x86/pmu.c
> +++ b/x86/pmu.c
> @@ -992,7 +992,7 @@ int main(int ac, char **av)
>  	printf("PMU version:         %d\n", pmu.version);
>  	printf("GP counters:         %d\n", pmu.nr_gp_counters);
>  	printf("GP counter width:    %d\n", pmu.gp_counter_width);
> -	printf("Mask length:         %d\n", pmu.gp_counter_mask_length);
> +	printf("Event Mask length:   %d\n", pmu.arch_event_mask_length);
>  	printf("Fixed counters:      %d\n", pmu.nr_fixed_counters);
>  	printf("Fixed counter width: %d\n", pmu.fixed_counter_width);
>  

-- 
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WARNING: multiple messages have this Message-ID (diff)
From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: "Sean Christopherson" <seanjc@google.com>,
	"Andrew Jones" <andrew.jones@linux.dev>,
	"Janosch Frank" <frankja@linux.ibm.com>,
	"Claudio Imbrenda" <imbrenda@linux.ibm.com>,
	"Nico Böhr" <nrb@linux.ibm.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>
Cc: kvm-riscv@lists.infradead.org, linux-s390@vger.kernel.org,
	kvm@vger.kernel.org
Subject: Re: [kvm-unit-tests PATCH 08/16] x86/pmu: Rename gp_counter_mask_length to arch_event_mask_length
Date: Tue, 10 Jun 2025 15:22:38 +0800	[thread overview]
Message-ID: <303a9aaa-eb52-47b2-af05-32df320dc52b@linux.intel.com> (raw)
In-Reply-To: <20250529221929.3807680-9-seanjc@google.com>


On 5/30/2025 6:19 AM, Sean Christopherson wrote:
> Rename gp_counter_mask_length to arch_event_mask_length to reflect what
> the field actually tracks.  The availablity of architectural events has
> nothing to do with the GP counters themselves.
>
> No functional change intended.
>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
>  lib/x86/pmu.c | 4 ++--
>  lib/x86/pmu.h | 2 +-
>  x86/pmu.c     | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c
> index 599168ac..b97e2c4a 100644
> --- a/lib/x86/pmu.c
> +++ b/lib/x86/pmu.c
> @@ -18,7 +18,7 @@ void pmu_init(void)
>  
>  		pmu.nr_gp_counters = (cpuid_10.a >> 8) & 0xff;
>  		pmu.gp_counter_width = (cpuid_10.a >> 16) & 0xff;
> -		pmu.gp_counter_mask_length = (cpuid_10.a >> 24) & 0xff;
> +		pmu.arch_event_mask_length = (cpuid_10.a >> 24) & 0xff;
>  
>  		/* CPUID.0xA.EBX bit is '1' if a counter is NOT available. */
>  		pmu.arch_event_available = ~cpuid_10.b;

Better to change to "pmu.arch_event_available = ~cpuid_10.b &
(BIT(pmu.arch_event_mask_length) - 1)" to follow SDM. Some newly introduced
architectural events like topdown metrics events doesn't exist on older
platforms.


> @@ -50,7 +50,7 @@ void pmu_init(void)
>  			pmu.msr_gp_event_select_base = MSR_K7_EVNTSEL0;
>  		}
>  		pmu.gp_counter_width = PMC_DEFAULT_WIDTH;
> -		pmu.gp_counter_mask_length = pmu.nr_gp_counters;
> +		pmu.arch_event_mask_length = pmu.nr_gp_counters;
>  		pmu.arch_event_available = (1u << pmu.nr_gp_counters) - 1;
>  
>  		if (this_cpu_has_perf_global_status()) {
> diff --git a/lib/x86/pmu.h b/lib/x86/pmu.h
> index d0ad280a..c7dc68c1 100644
> --- a/lib/x86/pmu.h
> +++ b/lib/x86/pmu.h
> @@ -63,7 +63,7 @@ struct pmu_caps {
>  	u8 fixed_counter_width;
>  	u8 nr_gp_counters;
>  	u8 gp_counter_width;
> -	u8 gp_counter_mask_length;
> +	u8 arch_event_mask_length;
>  	u32 arch_event_available;
>  	u32 msr_gp_counter_base;
>  	u32 msr_gp_event_select_base;
> diff --git a/x86/pmu.c b/x86/pmu.c
> index 0ce34433..63eae3db 100644
> --- a/x86/pmu.c
> +++ b/x86/pmu.c
> @@ -992,7 +992,7 @@ int main(int ac, char **av)
>  	printf("PMU version:         %d\n", pmu.version);
>  	printf("GP counters:         %d\n", pmu.nr_gp_counters);
>  	printf("GP counter width:    %d\n", pmu.gp_counter_width);
> -	printf("Mask length:         %d\n", pmu.gp_counter_mask_length);
> +	printf("Event Mask length:   %d\n", pmu.arch_event_mask_length);
>  	printf("Fixed counters:      %d\n", pmu.nr_fixed_counters);
>  	printf("Fixed counter width: %d\n", pmu.fixed_counter_width);
>  

  reply	other threads:[~2025-06-10  7:22 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-29 22:19 [kvm-unit-tests PATCH 00/16] x86: Add CPUID properties, clean up related code Sean Christopherson
2025-05-29 22:19 ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 01/16] lib: Add and use static_assert() convenience wrappers Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-30  6:03   ` Andrew Jones
2025-05-30  6:03     ` Andrew Jones
2025-05-30  9:01   ` Janosch Frank
2025-05-30  9:01     ` Janosch Frank
2025-06-10  6:04   ` Mi, Dapeng
2025-06-10  6:04     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 02/16] x86: Encode X86_FEATURE_* definitions using a structure Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  6:08   ` Mi, Dapeng
2025-06-10  6:08     ` Mi, Dapeng
2025-06-10 13:56     ` Sean Christopherson
2025-06-10 13:56       ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 03/16] x86: Add X86_PROPERTY_* framework to retrieve CPUID values Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  6:14   ` Mi, Dapeng
2025-06-10  6:14     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 04/16] x86: Use X86_PROPERTY_MAX_VIRT_ADDR in is_canonical() Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  6:16   ` Mi, Dapeng
2025-06-10  6:16     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 05/16] x86: Implement get_supported_xcr0() using X86_PROPERTY_SUPPORTED_XCR0_{LO,HI} Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  6:18   ` Mi, Dapeng
2025-06-10  6:18     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 06/16] x86: Add and use X86_PROPERTY_INTEL_PT_NR_RANGES Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  6:21   ` Mi, Dapeng
2025-06-10  6:21     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 07/16] x86/pmu: Rename pmu_gp_counter_is_available() to pmu_arch_event_is_available() Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  7:09   ` Mi, Dapeng
2025-06-10  7:09     ` Mi, Dapeng
2025-06-10 16:16     ` Sean Christopherson
2025-06-10 16:16       ` Sean Christopherson
2025-06-11  0:41       ` Mi, Dapeng
2025-06-11  0:41         ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 08/16] x86/pmu: Rename gp_counter_mask_length to arch_event_mask_length Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  7:22   ` Mi, Dapeng [this message]
2025-06-10  7:22     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 09/16] x86/pmu: Mark all arch events as available on AMD Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 10/16] x86/pmu: Use X86_PROPERTY_PMU_* macros to retrieve PMU information Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  7:29   ` Mi, Dapeng
2025-06-10  7:29     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 11/16] x86/sev: Use VC_VECTOR from processor.h Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10  7:25   ` Mi, Dapeng
2025-06-10  7:25     ` Mi, Dapeng
2025-05-29 22:19 ` [kvm-unit-tests PATCH 12/16] x86/sev: Skip the AMD SEV test if SEV is unsupported/disabled Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 13/16] x86/sev: Define and use X86_FEATURE_* flags for CPUID 0x8000001F Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 14/16] x86/sev: Use X86_PROPERTY_SEV_C_BIT to get the AMD SEV C-bit location Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-29 22:19 ` [kvm-unit-tests PATCH 15/16] x86/sev: Use amd_sev_es_enabled() to detect if SEV-ES is enabled Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-05-30 16:22   ` Liam Merwick
2025-05-30 16:22     ` Liam Merwick
2025-05-29 22:19 ` [kvm-unit-tests PATCH 16/16] x86: Move SEV MSR definitions to msr.h Sean Christopherson
2025-05-29 22:19   ` Sean Christopherson
2025-06-10 19:42 ` [kvm-unit-tests PATCH 00/16] x86: Add CPUID properties, clean up related code Sean Christopherson
2025-06-10 19:42   ` Sean Christopherson

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