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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.2 (3.50.2-1.fc39) MIME-Version: 1.0 On Thu, 2024-03-14 at 16:33 +0100, Jan Beulich wrote: > On 14.03.2024 15:45, Andrew Cooper wrote: > > On 13/03/2024 5:27 pm, Andrew Cooper wrote: > > > Start cleaning it up with ffs() and friends.=C2=A0 Across the board, > > > this adds: > > >=20 > > > =C2=A0* Functioning bitops without arch-specific asm > >=20 > > It turns out that RISC-V doesn't have a CLZ instruction in the base > > ISA.=C2=A0 As a consequence, __builtin_ffs() emits a library call to > > ffs() on > > GCC, or a de Bruijn sequence on Clang. > >=20 > > The optional Zbb extension adds a CLZ instruction, after which > > __builtin_ffs() emits a very simple sequence. > >=20 > > This leaves us with several options. > >=20 > > 1) Put generic_ffs() back in, although if we do this then it's > > going to > > be out-of-line in lib/ where it can be mostly ignored. > >=20 > > 2) Require Zbb for Xen. > >=20 > > 3) Alternative it up with Zbb or generic_ffs(). > >=20 > >=20 > > I've got half a mind to do 1) irrespective.=C2=A0 It's mostly just > > shuffling > > logic out of bitops.h into lib/. >=20 > Yes. Might also help with the bi-sectability issue you faced. >=20 > > I also think we should do option 2 for RISCV.=C2=A0 Given the > > instruction > > groups that H does mandate, it's unrealistic to expect that such a > > chip > > wouldn't support Zbb/etc. >=20 > I'm not so sure here. If to look at available specs of CPUs with H, then, for example, SiFive P600 series family doesn't support Zbb extenstion: https://sifive.cdn.prismic.io/sifive/7be0420e-dac1-4558-85bc-50c7a10787e7_p= 600_datasheet.pdf But I asked a team who are producing CPU with H support and they have Zbb extenstion. >=20 > > Also, getting full alternatives working is yet-more work that's not > > trivial at this point in RISCV's development.=C2=A0 I think it is > > entirely > > reasonable to avoid this work for now, and make it a problem for > > anyone > > who has an H-capable Zbb-incapable system.=C2=A0 (with a strong > > implication > > that this is work that probably never needs to be done.) >=20 > That's definitely for later. Considering that we are mainly using QEMU and it provides Zbb extension we can just update -march, and that a real h/w where I can ask to test a code also support this extenstion I will update riscv/booting.txt and update -march. ~ Oleksii