From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Stuebner Subject: Re: [PATCH v6 3/8] clk: rockchip: rk3399: add ddrc clock support Date: Fri, 19 Aug 2016 14:26:34 +0200 Message-ID: <3094872.dpWUHq2nPG@phil> References: <1471386989-9541-1-git-send-email-hl@rock-chips.com> <1471386989-9541-4-git-send-email-hl@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1471386989-9541-4-git-send-email-hl@rock-chips.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Lin Huang Cc: tixy@linaro.org, mark.rutland@arm.com, dbasehore@chromium.org, cw00.choi@samsung.com, mturquette@baylibre.com, typ@rock-chips.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, sudeep.holla@arm.com, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: linux-pm@vger.kernel.org QW0gTWl0dHdvY2gsIDE3LiBBdWd1c3QgMjAxNiwgMDY6MzY6MjQgQ0VTVCBzY2hyaWViIExpbiBI dWFuZzoKPiBhZGQgZGRyYyBjbG9jayBzZXR0aW5nLCBzbyB3ZSBjYW4gZG8gZGRyIGZyZXF1ZW5j eQo+IHNjYWxpbmcgb24gcmszMzk5IHBsYXRmb3JtIGluIGZ1dHVyZS4KPiAKPiBTaWduZWQtb2Zm LWJ5OiBMaW4gSHVhbmcgPGhsQHJvY2stY2hpcHMuY29tPgo+IC0tLQo+IENoYW5nZXMgaW4gdjY6 Cj4gLSBOb25lCj4gCj4gQ2hhbmdlcyBpbiB2NToKPiAtIGZpdCBmb3IgdGhlIGRkciB0eXBlCj4g Cj4gQ2hhbmdlcyBpbiB2NDoKPiAtIE5vbmUKPiAKPiBDaGFuZ2VzIGluIHYzOgo+IC0gTm9uZQo+ IAo+IENoYW5nZXMgaW4gdjI6Cj4gLSByZW1vdmUgY2xrX2RkcmNfZHBsbF9zcmMgZnJvbSBjcml0 aWNhbCBjbG9jayBsaXN0Cj4gCj4gQ2hhbmdlcyBpbiB2MToKPiAtIHJlbW92ZSBkZHJjIHNvdXJj ZSBDTEtfSUdOT1JFX1VOVVNFRCBmbGFnCj4gLSBtb3ZlIGNsa19kZHJjIGFuZCBjbGtfZGRyY19k cGxsX3NyYyB0byBjcml0aWNhbAo+IAo+ICBkcml2ZXJzL2Nsay9yb2NrY2hpcC9jbGstcmszMzk5 LmMgfCAxOSArKysrKysrKysrKysrKysrKysrCj4gIDEgZmlsZSBjaGFuZ2VkLCAxOSBpbnNlcnRp b25zKCspCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvY2xrL3JvY2tjaGlwL2Nsay1yazMzOTku Ywo+IGIvZHJpdmVycy9jbGsvcm9ja2NoaXAvY2xrLXJrMzM5OS5jIGluZGV4IGU0NDVjZDYuLjAx ZDQ5NDUgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9jbGsvcm9ja2NoaXAvY2xrLXJrMzM5OS5jCj4g KysrIGIvZHJpdmVycy9jbGsvcm9ja2NoaXAvY2xrLXJrMzM5OS5jCj4gQEAgLTEyMCw2ICsxMjAs MTAgQEAgUE5BTUUobXV4X2FybWNsa2JfcCkJCQkJPSB7IAoiY2xrX2NvcmVfYl9scGxsX3NyYyIs Cj4gIAkJCQkJCSAgICAiY2xrX2NvcmVfYl9icGxsX3NyYyIsCj4gIAkJCQkJCSAgICAiY2xrX2Nv cmVfYl9kcGxsX3NyYyIsCj4gIAkJCQkJCSAgICAiY2xrX2NvcmVfYl9ncGxsX3NyYyIgfTsKPiAr UE5BTUUobXV4X2RkcmNsa19wKQkJCQk9IHsgImNsa19kZHJjX2xwbGxfc3JjIiwKPiArCQkJCQkJ ICAgICJjbGtfZGRyY19icGxsX3NyYyIsCj4gKwkJCQkJCSAgICAiY2xrX2RkcmNfZHBsbF9zcmMi LAo+ICsJCQkJCQkgICAgImNsa19kZHJjX2dwbGxfc3JjIiB9Owo+ICBQTkFNRShtdXhfYWNsa19j Y2lfcCkJCQkJPSB7ICJjcGxsX2FjbGtfY2NpX3NyYyIsCj4gIAkJCQkJCSAgICAiZ3BsbF9hY2xr X2NjaV9zcmMiLAo+ICAJCQkJCQkgICAgIm5wbGxfYWNsa19jY2lfc3JjIiwKPiBAQCAtMTM3OSw2 ICsxMzgzLDE4IEBAIHN0YXRpYyBzdHJ1Y3Qgcm9ja2NoaXBfY2xrX2JyYW5jaAo+IHJrMzM5OV9j bGtfYnJhbmNoZXNbXSBfX2luaXRkYXRhID0geyBDT01QT1NJVEVfTk9NVVgoMCwgImNsa190ZXN0 IiwKPiAiY2xrX3Rlc3RfcHJlIiwgQ0xLX0lHTk9SRV9VTlVTRUQsIFJLMzM2OF9DTEtTRUxfQ09O KDU4KSwgMCwgNSwgREZMQUdTLAo+ICAJCQlSSzMzNjhfQ0xLR0FURV9DT04oMTMpLCAxMSwgR0ZM QUdTKSwKPiArCj4gKwkvKiBkZHJjICovCj4gKwlHQVRFKDAsICJjbGtfZGRyY19scGxsX3NyYyIs ICJscGxsIiwgMCwgUkszMzk5X0NMS0dBVEVfQ09OKDMpLAo+ICsJICAgICAwLCBHRkxBR1MpLAo+ ICsJR0FURSgwLCAiY2xrX2RkcmNfYnBsbF9zcmMiLCAiYnBsbCIsIDAsIFJLMzM5OV9DTEtHQVRF X0NPTigzKSwKPiArCSAgICAgMSwgR0ZMQUdTKSwKPiArCUdBVEUoMCwgImNsa19kZHJjX2RwbGxf c3JjIiwgImRwbGwiLCAwLCBSSzMzOTlfQ0xLR0FURV9DT04oMyksCj4gKwkgICAgIDIsIEdGTEFH UyksCj4gKwlHQVRFKDAsICJjbGtfZGRyY19ncGxsX3NyYyIsICJncGxsIiwgMCwgUkszMzk5X0NM S0dBVEVfQ09OKDMpLAo+ICsJICAgICAzLCBHRkxBR1MpLAo+ICsJQ09NUE9TSVRFX0REUkNMSyhT Q0xLX0REUkMsICJjbGtfZGRyYyIsIG11eF9kZHJjbGtfcCwgMCwKCkkgdGhpbmsgSSdkIGxpa2Ug dG8gaGF2ZSB0aGUgY2xvY2sgYWxzbyBuYW1lZCBzY2xrX2RkcmMgOi0pCgpPdGhlcndpc2UgdGhh dCBsb29rcyBmaW5lCgoKSGVpa28KX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRl c2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8v ZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: heiko@sntech.de (Heiko Stuebner) Date: Fri, 19 Aug 2016 14:26:34 +0200 Subject: [PATCH v6 3/8] clk: rockchip: rk3399: add ddrc clock support In-Reply-To: <1471386989-9541-4-git-send-email-hl@rock-chips.com> References: <1471386989-9541-1-git-send-email-hl@rock-chips.com> <1471386989-9541-4-git-send-email-hl@rock-chips.com> Message-ID: <3094872.dpWUHq2nPG@phil> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Am Mittwoch, 17. August 2016, 06:36:24 CEST schrieb Lin Huang: > add ddrc clock setting, so we can do ddr frequency > scaling on rk3399 platform in future. > > Signed-off-by: Lin Huang > --- > Changes in v6: > - None > > Changes in v5: > - fit for the ddr type > > Changes in v4: > - None > > Changes in v3: > - None > > Changes in v2: > - remove clk_ddrc_dpll_src from critical clock list > > Changes in v1: > - remove ddrc source CLK_IGNORE_UNUSED flag > - move clk_ddrc and clk_ddrc_dpll_src to critical > > drivers/clk/rockchip/clk-rk3399.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/clk/rockchip/clk-rk3399.c > b/drivers/clk/rockchip/clk-rk3399.c index e445cd6..01d4945 100644 > --- a/drivers/clk/rockchip/clk-rk3399.c > +++ b/drivers/clk/rockchip/clk-rk3399.c > @@ -120,6 +120,10 @@ PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", > "clk_core_b_bpll_src", > "clk_core_b_dpll_src", > "clk_core_b_gpll_src" }; > +PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", > + "clk_ddrc_bpll_src", > + "clk_ddrc_dpll_src", > + "clk_ddrc_gpll_src" }; > PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", > "gpll_aclk_cci_src", > "npll_aclk_cci_src", > @@ -1379,6 +1383,18 @@ static struct rockchip_clk_branch > rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_test", > "clk_test_pre", CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, > RK3368_CLKGATE_CON(13), 11, GFLAGS), > + > + /* ddrc */ > + GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3), > + 0, GFLAGS), > + GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3), > + 1, GFLAGS), > + GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3), > + 2, GFLAGS), > + GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3), > + 3, GFLAGS), > + COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrclk_p, 0, I think I'd like to have the clock also named sclk_ddrc :-) Otherwise that looks fine Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754280AbcHSM11 (ORCPT ); Fri, 19 Aug 2016 08:27:27 -0400 Received: from gloria.sntech.de ([95.129.55.99]:41910 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753990AbcHSM10 (ORCPT ); Fri, 19 Aug 2016 08:27:26 -0400 From: Heiko Stuebner To: Lin Huang Cc: myungjoo.ham@samsung.com, tixy@linaro.org, mark.rutland@arm.com, typ@rock-chips.com, linux-rockchip@lists.infradead.org, airlied@linux.ie, mturquette@baylibre.com, dbasehore@chromium.org, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, sudeep.holla@arm.com, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mark.yao@rock-chips.com Subject: Re: [PATCH v6 3/8] clk: rockchip: rk3399: add ddrc clock support Date: Fri, 19 Aug 2016 14:26:34 +0200 Message-ID: <3094872.dpWUHq2nPG@phil> User-Agent: KMail/5.2.3 (Linux/4.6.0-1-amd64; KDE/5.23.0; x86_64; ; ) In-Reply-To: <1471386989-9541-4-git-send-email-hl@rock-chips.com> References: <1471386989-9541-1-git-send-email-hl@rock-chips.com> <1471386989-9541-4-git-send-email-hl@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Mittwoch, 17. August 2016, 06:36:24 CEST schrieb Lin Huang: > add ddrc clock setting, so we can do ddr frequency > scaling on rk3399 platform in future. > > Signed-off-by: Lin Huang > --- > Changes in v6: > - None > > Changes in v5: > - fit for the ddr type > > Changes in v4: > - None > > Changes in v3: > - None > > Changes in v2: > - remove clk_ddrc_dpll_src from critical clock list > > Changes in v1: > - remove ddrc source CLK_IGNORE_UNUSED flag > - move clk_ddrc and clk_ddrc_dpll_src to critical > > drivers/clk/rockchip/clk-rk3399.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/clk/rockchip/clk-rk3399.c > b/drivers/clk/rockchip/clk-rk3399.c index e445cd6..01d4945 100644 > --- a/drivers/clk/rockchip/clk-rk3399.c > +++ b/drivers/clk/rockchip/clk-rk3399.c > @@ -120,6 +120,10 @@ PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", > "clk_core_b_bpll_src", > "clk_core_b_dpll_src", > "clk_core_b_gpll_src" }; > +PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", > + "clk_ddrc_bpll_src", > + "clk_ddrc_dpll_src", > + "clk_ddrc_gpll_src" }; > PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", > "gpll_aclk_cci_src", > "npll_aclk_cci_src", > @@ -1379,6 +1383,18 @@ static struct rockchip_clk_branch > rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_test", > "clk_test_pre", CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, > RK3368_CLKGATE_CON(13), 11, GFLAGS), > + > + /* ddrc */ > + GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3), > + 0, GFLAGS), > + GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3), > + 1, GFLAGS), > + GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3), > + 2, GFLAGS), > + GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3), > + 3, GFLAGS), > + COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrclk_p, 0, I think I'd like to have the clock also named sclk_ddrc :-) Otherwise that looks fine Heiko