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From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: Quentin Schulz , Kever Yang , u-boot@lists.u-boot-project.org Cc: Simon Glass , Lukasz Majewski , Tom Rini , Alexey Charkov , u-boot@lists.u-boot-project.org, Jonas Karlman , Jonas Karlman Subject: Re: [PATCH 0/4] rockchip: Always init clocks in SPL build for RK35xx Date: Tue, 08 Sep 2026 13:26:06 +0200 Message-ID: <3099454.C4sosBPzcN@diego> In-Reply-To: <20260804002643.2308515-1-jonas@kwiboo.se> References: <20260804002643.2308515-1-jonas@kwiboo.se> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Am Dienstag, 4. August 2026, 02:26:38 Mitteleurop=C3=A4ische Sommerzeit sch= rieb Jonas Karlman: > This series flag clock drivers for probe after bind in SPL builds for > a few RK35xx SoCs that require core PLLs and clocks to be initialized at > an early phase. >=20 > This should help e.g. ensure SPLL is initialized correctly on RK3588 and > CPU core rate is initialized on RK3576 when booting from RAM/USB. >=20 > The series may possible depend on the series "rockchip: Miscellaneous > RK35xx clock fixes" [1] for a clean apply. >=20 > [1] https://patchwork.ozlabs.org/cover/2278934/ Tested-by: Heiko Stuebner This and the misc fixes series together make my DSI panel work again, which seemingly broke somewhere in between. Thanks Heiko