From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-189.mta0.migadu.com (out-189.mta0.migadu.com [91.218.175.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E12C14AD15 for ; Thu, 25 Apr 2024 15:22:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.189 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714058567; cv=none; b=W5bpRFH+YqCQlx3iiSXYVo2NnpRHi1aaFJ88lSCy5FCG+6gUYpZWoZ65HFS1kpDf3vAwLvrKX9tLbc1Rvi3/b4mqzOsGAxeZc47Fk2xj81+nrywVXtZXD+4nQkqLIerRRTEnyKw08hyA4uBWbVMiMvmIKCqpDcPmAFzUaNIiBvY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714058567; c=relaxed/simple; bh=Zp1XztddXWSkzPRERD8uSH+GGbnPFecGU8R3FZDOubA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=GxrowsKn4TAsze1TeEu8EwZq5HQL/FUBMVxzHYtRdIcrbdiPRYAHVhhRgqQS4dFJCcKpq106dLAY3SeOqD3DFcrJVWooWt0VVdmIuYZbYjJl6aVoEk9iFxy7dFasLI/LWruuYDh3lU99NhEVLOVnjU4t4oyDIVVm2yGvnLeA/aU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=lGFhM1vP; arc=none smtp.client-ip=91.218.175.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="lGFhM1vP" Message-ID: <309b52e6-c206-4811-b14e-db5206adf902@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1714058563; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yLi5S9z+IggrVLuyc1ioiY20GXVGW50A1sm+DJHyEzY=; b=lGFhM1vPlM2U00uPhd1FsTRiffFXhMa+qiOudGzBGWJC5ejhSmPE4Wr+9Go5rHD1AeM+GF tBfSckSzzxYSJq4idyH1eMnfxoytxkL4evZVUUKA8OQNOZGTUA7a2iM/jTINOmelMwu1qf RktX9bHZPJgLsPfojIwXR3wSNSvBjwA= Date: Thu, 25 Apr 2024 11:22:40 -0400 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: pinctrl: zynqmp: Valid pin muxings cannot be configured To: Michal Simek , "linux-gpio@vger.kernel.org" Cc: Linus Walleij , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" References: <5bb0dc7e-4c89-4f3d-abc6-41ae9ded5ae9@linux.dev> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 4/24/24 02:22, Michal Simek wrote: > Hi Sean, > > On 4/24/24 01:04, Sean Anderson wrote: >> Hi Michal, >> >> I was looking to upstream one of our ZynqMP boards, and I ran into an >> issue with the pinmuxing. We use almost all of the I/Os, so everything >> is tightly packed into the MIO. For example, we have the QSPI on MIO0 to >> MIO5, and MIO6 to MIO11 are used for SPI1. However, I cannot select this >> configuration using the pinmux driver. I am using the following >> configuration: >> >> pinctrl_qspi_default: qspi-default { >> mux { >> groups = "qspi0_0_grp"; >> function = "qspi0"; >> }; >> >> mux-cs { >> groups = "qspi_ss_0_grp"; >> function = "qspi_ss"; >> }; >> }; >> >> pinctrl_spi1_default: spi1-default { >> mux { >> groups = "spi1_0_grp"; >> function = "spi1"; >> }; >> >> mux-cs { >> groups = "spi1_ss_0_grp", "spi1_ss_1_grp"; >> function = "spi1_ss"; >> }; >> }; >> >> But I get the following errors on boot: >> >> [ 4.261739] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: pin MIO8 already requested by ff050000.spi; cannot claim for ff0f0000.spi >> [ 4.274506] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: error -EINVAL: pin-8 (ff0f0000.spi) >> [ 4.283789] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: error -EINVAL: could not request pin 8 (MIO8) from group qspi0_0_grp on device zynqmp_pinctrl >> >> This is because the qspi0_0_grp and spi1_0_grp groups overlap: >> >> group: qspi0_0_grp >> pin 0 (MIO0) >> pin 1 (MIO1) >> pin 2 (MIO2) >> pin 3 (MIO3) >> pin 4 (MIO4) >> pin 8 (MIO8) >> pin 9 (MIO9) >> pin 10 (MIO10) >> pin 11 (MIO11) >> pin 12 (MIO12) >> >> group: qspi_ss_0_grp >> pin 5 (MIO5) >> pin 7 (MIO7) >> >> group: qspi_fbclk_0_grp >> pin 6 (MIO6) >> >> group: spi1_0_grp >> pin 6 (MIO6) >> pin 10 (MIO10) >> pin 11 (MIO11) >> >> group: spi1_ss_0_grp >> pin 9 (MIO9) >> >> group: spi1_ss_1_grp >> pin 8 (MIO8) >> >> group: spi1_ss_2_grp >> pin 7 (MIO7) >> >> However, we are not using the "upper" pins of the QSPI device. >> Therefore, these pins should not be included in the qspi0_0_grp. This >> stems from the driver placing all possible pins into a function's group, >> even though each pin can be muxed individially and it is not necessary >> to mux all pins for full functionality. > > Correct. These configurations were not consider at that time when code > was written. The same issue is there if you want to combine pins from > different groups. IIRC uart rx via MIOX and tx not from MIOX+1. > >> >> I think it would be better to have a single group for each pin: >> >> pinctrl_qspi_default: qspi-default { >> mux { >> groups = "mio0", "mio1", "mio2", "mio3", "mio4"; >> function = "qspi0"; >> }; >> >> mux-cs { >> groups = "mio5"; >> function = "qspi_ss"; >> }; >> }; >> >> pinctrl_spi1_default: spi1-default { >> mux { >> groups = "mio6", "mio10", "mio11"; >> function = "spi1"; >> }; >> >> mux-cs { >> groups = "mio8", "mio9"; >> function = "spi1_ss"; >> }; >> }; >> >> This allows the full functionality of this chip to be configured. Does >> that sound good? I can send a patch to this effect if you agree. > > The only question is if this can be done without changing TF-A code > because we are running out of space in OCM for it. I think this can be done just in the Linux driver. This would also be convenient because then it will work regardless of the firmware. > Just a generic question to your problem. It doesn't sound like a > dynamic case. You have static assignment for pins which likely won't > change over lifecycle. QSPI can be even boot device. Do you really > need to describe pins via DT that it is not enough to have them > configured via psu_init directly? > > Driver has been developed for i2c bus recovery via gpio which was the > main application. Right now Kria SOM is using it for carrier card pins > configuration. And Kria is pretty much only platform where this is > regularly tested. This is just following the example of the ZCU102. But you're right, these pin configurations are static (excepting I2C). --Sean From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4ADD3C4345F for ; Thu, 25 Apr 2024 15:29:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=leOZ+TWRLg+M6ZkPNTOAkIo39iZxte0G9aeeblZFVXw=; b=X9ul2i1W0nMLYG Ol0JwnHk/c48mFwqTTtuP71nrFBZFypqdg6M/mTLgp88w6WyvezofjFaR1yS2gVwsj6TNpJi6gEiQ rQb8slJNFaJUdrDIWXrvYeKVNDzLAItGRln4oX6dR9yJ5jctPqklmIbn1yRUyOvIrmeJAccxC1wYL iFJU3Dgc8XcgTinSVxTxZztQp3qDbxrLnnPEBXP7sRpqdTih0kUZLrMgoulTUvSKxH1dvdHB1LhMg 7xG/Yp8el4Hquy3zBAuZvUOltdeC6QN6YPfbeO7GRAMqTXwOEkfvJDg1aLBrRsq5drKALUh9+FSQE DayQwnq8iLg4rqb9C5Jw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s012Z-000000098uW-0RfI; Thu, 25 Apr 2024 15:29:39 +0000 Received: from out-175.mta0.migadu.com ([2001:41d0:1004:224b::af]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s012W-000000098s8-2EfC for linux-arm-kernel@lists.infradead.org; Thu, 25 Apr 2024 15:29:38 +0000 Message-ID: <309b52e6-c206-4811-b14e-db5206adf902@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1714058563; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yLi5S9z+IggrVLuyc1ioiY20GXVGW50A1sm+DJHyEzY=; b=lGFhM1vPlM2U00uPhd1FsTRiffFXhMa+qiOudGzBGWJC5ejhSmPE4Wr+9Go5rHD1AeM+GF tBfSckSzzxYSJq4idyH1eMnfxoytxkL4evZVUUKA8OQNOZGTUA7a2iM/jTINOmelMwu1qf RktX9bHZPJgLsPfojIwXR3wSNSvBjwA= Date: Thu, 25 Apr 2024 11:22:40 -0400 MIME-Version: 1.0 Subject: Re: pinctrl: zynqmp: Valid pin muxings cannot be configured To: Michal Simek , "linux-gpio@vger.kernel.org" Cc: Linus Walleij , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" References: <5bb0dc7e-4c89-4f3d-abc6-41ae9ded5ae9@linux.dev> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson In-Reply-To: X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240425_082936_865441_C2CBE059 X-CRM114-Status: GOOD ( 28.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 4/24/24 02:22, Michal Simek wrote: > Hi Sean, > > On 4/24/24 01:04, Sean Anderson wrote: >> Hi Michal, >> >> I was looking to upstream one of our ZynqMP boards, and I ran into an >> issue with the pinmuxing. We use almost all of the I/Os, so everything >> is tightly packed into the MIO. For example, we have the QSPI on MIO0 to >> MIO5, and MIO6 to MIO11 are used for SPI1. However, I cannot select this >> configuration using the pinmux driver. I am using the following >> configuration: >> >> pinctrl_qspi_default: qspi-default { >> mux { >> groups = "qspi0_0_grp"; >> function = "qspi0"; >> }; >> >> mux-cs { >> groups = "qspi_ss_0_grp"; >> function = "qspi_ss"; >> }; >> }; >> >> pinctrl_spi1_default: spi1-default { >> mux { >> groups = "spi1_0_grp"; >> function = "spi1"; >> }; >> >> mux-cs { >> groups = "spi1_ss_0_grp", "spi1_ss_1_grp"; >> function = "spi1_ss"; >> }; >> }; >> >> But I get the following errors on boot: >> >> [ 4.261739] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: pin MIO8 already requested by ff050000.spi; cannot claim for ff0f0000.spi >> [ 4.274506] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: error -EINVAL: pin-8 (ff0f0000.spi) >> [ 4.283789] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: error -EINVAL: could not request pin 8 (MIO8) from group qspi0_0_grp on device zynqmp_pinctrl >> >> This is because the qspi0_0_grp and spi1_0_grp groups overlap: >> >> group: qspi0_0_grp >> pin 0 (MIO0) >> pin 1 (MIO1) >> pin 2 (MIO2) >> pin 3 (MIO3) >> pin 4 (MIO4) >> pin 8 (MIO8) >> pin 9 (MIO9) >> pin 10 (MIO10) >> pin 11 (MIO11) >> pin 12 (MIO12) >> >> group: qspi_ss_0_grp >> pin 5 (MIO5) >> pin 7 (MIO7) >> >> group: qspi_fbclk_0_grp >> pin 6 (MIO6) >> >> group: spi1_0_grp >> pin 6 (MIO6) >> pin 10 (MIO10) >> pin 11 (MIO11) >> >> group: spi1_ss_0_grp >> pin 9 (MIO9) >> >> group: spi1_ss_1_grp >> pin 8 (MIO8) >> >> group: spi1_ss_2_grp >> pin 7 (MIO7) >> >> However, we are not using the "upper" pins of the QSPI device. >> Therefore, these pins should not be included in the qspi0_0_grp. This >> stems from the driver placing all possible pins into a function's group, >> even though each pin can be muxed individially and it is not necessary >> to mux all pins for full functionality. > > Correct. These configurations were not consider at that time when code > was written. The same issue is there if you want to combine pins from > different groups. IIRC uart rx via MIOX and tx not from MIOX+1. > >> >> I think it would be better to have a single group for each pin: >> >> pinctrl_qspi_default: qspi-default { >> mux { >> groups = "mio0", "mio1", "mio2", "mio3", "mio4"; >> function = "qspi0"; >> }; >> >> mux-cs { >> groups = "mio5"; >> function = "qspi_ss"; >> }; >> }; >> >> pinctrl_spi1_default: spi1-default { >> mux { >> groups = "mio6", "mio10", "mio11"; >> function = "spi1"; >> }; >> >> mux-cs { >> groups = "mio8", "mio9"; >> function = "spi1_ss"; >> }; >> }; >> >> This allows the full functionality of this chip to be configured. Does >> that sound good? I can send a patch to this effect if you agree. > > The only question is if this can be done without changing TF-A code > because we are running out of space in OCM for it. I think this can be done just in the Linux driver. This would also be convenient because then it will work regardless of the firmware. > Just a generic question to your problem. It doesn't sound like a > dynamic case. You have static assignment for pins which likely won't > change over lifecycle. QSPI can be even boot device. Do you really > need to describe pins via DT that it is not enough to have them > configured via psu_init directly? > > Driver has been developed for i2c bus recovery via gpio which was the > main application. Right now Kria SOM is using it for carrier card pins > configuration. And Kria is pretty much only platform where this is > regularly tested. This is just following the example of the ZCU102. But you're right, these pin configurations are static (excepting I2C). --Sean _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel