From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C33EC433EF for ; Tue, 14 Jun 2022 16:27:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1KnZnn6Am2ms/f5qZSJM2gIaTu1RDwgx47vDR9y3WDg=; b=k5Brq/7Xl36OjY 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Heiko =?ISO-8859-1?Q?St=FCbner?= To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Dao Lu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Randy Dunlap , Rob Herring , Alexandre Ghiti , Qinglin Pan , Tsukasa OI , Jisheng Zhang , "open list:RISC-V ARCHITECTURE" , Dao Lu Subject: Re: [PATCH v2] arch/riscv: add Zihintpause support Date: Tue, 14 Jun 2022 18:26:51 +0200 Message-ID: <3113192.5fSG56mABF@diego> In-Reply-To: <20220524211954.1936117-1-daolu@rivosinc.com> References: <20220524211954.1936117-1-daolu@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220614_092714_484811_2ADE2E1A X-CRM114-Status: GOOD ( 21.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 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(vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D8F1C433EF for ; Tue, 14 Jun 2022 16:27:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238564AbiFNQ1G convert rfc822-to-8bit (ORCPT ); Tue, 14 Jun 2022 12:27:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343818AbiFNQ1C (ORCPT ); Tue, 14 Jun 2022 12:27:02 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2391C2EA1E for ; Tue, 14 Jun 2022 09:26:59 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1o19NU-0000yX-7r; Tue, 14 Jun 2022 18:26:52 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Dao Lu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Randy Dunlap , Rob Herring , Alexandre Ghiti , Qinglin Pan , Tsukasa OI , Jisheng Zhang , "open list:RISC-V ARCHITECTURE" , Dao Lu Subject: Re: [PATCH v2] arch/riscv: add Zihintpause support Date: Tue, 14 Jun 2022 18:26:51 +0200 Message-ID: <3113192.5fSG56mABF@diego> In-Reply-To: <20220524211954.1936117-1-daolu@rivosinc.com> References: <20220524211954.1936117-1-daolu@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, 24. Mai 2022, 23:19:50 CEST schrieb Dao Lu: > Implement support for the ZiHintPause extension. > > The PAUSE instruction is a HINT that indicates the current hart’s rate of > instruction retirement should be temporarily reduced or paused. > > Reviewed-by: Heiko Stuebner > Tested-by: Heiko Stuebner > Signed-off-by: Dao Lu > --- > > v1 -> v2: > Remove the usage of static branch, use PAUSE if toolchain supports it > > arch/riscv/Makefile | 4 ++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/vdso/processor.h | 8 +++++++- > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 2 ++ > 5 files changed, 15 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 7d81102cffd4..900a8fda1a2d 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > > +# Check if the toolchain supports Zihintpause extension > +toolchain-supports-zihintpause := $(call cc-option-yn, -march=$(riscv-march-y)_zihintpause) > +riscv-march-$(toolchain-supports-zihintpause) := $(riscv-march-y)_zihintpause > + > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > KBUILD_AFLAGS += -march=$(riscv-march-y) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 0734e42f74f2..caa9ee5459b4 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -52,6 +52,7 @@ extern unsigned long elf_hwcap; > */ > enum riscv_isa_ext_id { > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, svpbmt got merged meanwhile, so this patch needs a rebase onto 5.19-rc. One more nit below > + RISCV_ISA_EXT_ZIHINTPAUSE, > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h > index 134388cbaaa1..4de911a25051 100644 > --- a/arch/riscv/include/asm/vdso/processor.h > +++ b/arch/riscv/include/asm/vdso/processor.h > @@ -8,7 +8,13 @@ > > static inline void cpu_relax(void) > { > -#ifdef __riscv_muldiv > +#ifdef __riscv_zihintpause > + /* > + * Reduce instruction retirement. > + * This assumes the PC changes. > + */ > + __asm__ __volatile__ ("pause"); > +#elif __riscv_muldiv > int dummy; > /* In lieu of a halt instruction, induce a long-latency stall. */ > __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index ccb617791e56..89e563e9c4cc 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node) > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > }; > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1b2d42d7f589..37ff06682ae6 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -25,6 +25,7 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); > #endif > > + this is an unrelated change and also is adding an unneeded extra empty line. Heiko > /** > * riscv_isa_extension_base() - Get base extension word > * > @@ -192,6 +193,7 @@ void __init riscv_fill_hwcap(void) > set_bit(*ext - 'a', this_isa); > } else { > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); > + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); > } > #undef SET_ISA_EXT_MAP > } >