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[2001:4c4e:24cd:7200:f6bb:a872:344e:1a32]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f4634e5b8sm17552158f8f.6.2026.07.15.13.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 13:12:07 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: sashiko-reviews@lists.linux.dev Cc: dri-devel@lists.freedesktop.org Subject: Re: [PATCH 4/4] drm/amd/display: Don't use tiling flags anymore Date: Wed, 15 Jul 2026 22:12:06 +0200 Message-ID: <31315640.VsfAaAtOVx@timur-max> In-Reply-To: <20260715114238.856321F000E9@smtp.kernel.org> References: <20260715105757.13125-1-timur.kristof@gmail.com> <20260715105757.13125-5-timur.kristof@gmail.com> <20260715114238.856321F000E9@smtp.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2026. j=C3=BAlius 15., szerda 13:42:38 k=C3=B6z=C3=A9p-eur=C3=B3pai ny= =C3=A1ri id=C5=91 sashiko- bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential > issue(s) to consider: - [High] Removing the `tiling_flags` check in > `should_reset_plane` allows framebuffers with different DCC pitches or > dimensions (but identical modifiers) to bypass DRM atomic check validatio= n, > leading to hardware corruption and stale DML calculations during commit. = =2D- This is not an issue. DCC is not supported at all on GFX6-7 and is not=20 supported by the display engine on GFX8. The code does not advertise any=20 modifiers with DCC on GFX6-8 either. >=20 > --- Patch [4]: [PATCH 4/4] drm/amd/display: Don't use tiling flags anymore > --- commit b71fc193d0b1254508d4ef4e5b1e90decbcba27a > Author: Timur Krist=C3=B3f >=20 > drm/amd/display: Don't use tiling flags anymore >=20 > This commit removes all code from amdgpu_dm that dealt with tiling flags, > as all supported GPU generations now support DRM format modifiers. The > legacy non-DC display code still relies on tiling flags. >=20 > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index > > c643cc5428577..2f7388c47d02a 100644 > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >=20 > [ ... ] >=20 > > @@ -4279,7 +4277,6 @@ static void amdgpu_dm_commit_planes(struct > > drm_atomic_state *state,>=20 > > fill_dc_plane_info_and_addr( > > =09 > > dm->adev, new_plane_state, > >=20 > > - afb->tiling_flags, > >=20 > > &bundle->plane_infos[planes_count], > > &bundle->flip_addrs[planes_count].address, > > afb->tmz_surface); >=20 > [Severity: High] > Since the return value of fill_dc_plane_info_and_addr() is ignored here, > what happens if DCC validation fails due to missed dimension or pitch > changes? DCC is not supported by the display engine on GFX6-8 so there is no DCC=20 validation. >=20 > Could this result in a zero-filled plane_info structure being sent to the > hardware (for example, setting global_alpha to 0) and causing a black > screen? No, it couldn't. >=20 > [ ... ] >=20 > > @@ -6248,8 +6245,7 @@ static bool should_reset_plane(struct > > drm_atomic_state *state,>=20 > > new_afb =3D (struct amdgpu_framebuffer *)new_other_state- >fb; > > =09 > > /* Tiling and DCC changes also require bandwidth=20 updates. */ > >=20 > > - if (old_afb->tiling_flags !=3D new_afb->tiling_flags || > > - old_afb->base.modifier !=3D new_afb->base.modifier) > > + if (old_afb->base.modifier !=3D new_afb->base.modifier) > >=20 > > return true; > > =09 > > } >=20 > [Severity: High] > By removing the tiling_flags check here in should_reset_plane(), how do we > ensure that framebuffers with identical modifiers but different DCC pitch= es > or dimensions still trigger a validation reset? The tiling flags are no longer used because they are converted to modifiers= =2E=20 Therefore, removing the tiling flag check is not changing the behavior of t= he=20 code. As I explained above, DCC is not supported by this HW. Additionally, "identical modifiers but with different DCC pitches" would be= =20 illegal for DRM format modifiers. >=20 > If a user-space client flips between two framebuffers with the same format > and source rectangle, but different backing buffer dimensions, it seems > this might bypass DRM atomic check validation. How? >=20 > Could this lead to DC hardware being programmed using stale Display Mode > Logger (DML) calculations and watermarks, resulting in display corruption? How?