diff for duplicates of <3135535.HuDyCXIRmt@jernej-laptop>

diff --git a/a/1.txt b/N1/1.txt
index e1d98a7..e396b0f 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -2,105 +2,103 @@ Hi,
 
 Dne petek, 18. maj 2018 ob 17:09:40 CEST je Sergey Suloev napisal(a):
 > Hi, guys,
->=20
-> On 05/18/2018 05:46 PM, Jernej =C5=A0krabec wrote:
+> 
+> On 05/18/2018 05:46 PM, Jernej ?krabec wrote:
 > > Hi,
-> >=20
+> > 
 > > Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
 > >> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
 > >>> From: Jernej Skrabec <jernej.skrabec@siol.net>
-> >>>=20
+> >>> 
 > >>> Some SoCs with DW HDMI have multiple possible clock parents, like A64
 > >>> and R40.
-> >>>=20
+> >>> 
 > >>> Expand HDMI PHY clock driver to support second clock parent.
-> >>>=20
+> >>> 
 > >>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
 > >>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
 > >>> ---
 > >>> Changes for v2:
 > >>> - new patch
-> >>>=20
+> >>> 
 > >>>   drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h      |  9 ++-
 > >>>   drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c     | 33 ++++++++---
 > >>>   drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 89
 > >>>   ++++++++++++++++++++++-------- 3 files changed, 96 insertions(+), 35
 > >>>   deletions(-)
-> >>>=20
+> >>> 
 > >>> diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-> >>> b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 79154f0f674a..303189d66=
-02c
+> >>> b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 79154f0f674a..303189d6602c
 > >>> 100644
 > >>> --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
 > >>> +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
 > >>> @@ -98,7 +98,8 @@
-> >>>=20
+> >>> 
 > >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN		BIT(29)
 > >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN		BIT(28)
 > >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33	BIT(27)
-> >>>=20
+> >>> 
 > >>> -#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL	BIT(26)
 > >>> +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK	BIT(26)
 > >>> +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT	26
-> >>>=20
+> >>> 
 > >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN		BIT(25)
 > >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x)	((x) << 22)
 > >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x)	((x) << 20)
-> >>>=20
+> >>> 
 > >>> @@ -146,7 +147,7 @@
-> >>>=20
+> >>> 
 > >>>   struct sun8i_hdmi_phy;
-> >>>  =20
+> >>>   
 > >>>   struct sun8i_hdmi_phy_variant {
-> >>>=20
+> >>> 
 > >>> -	bool has_phy_clk;
 > >>> +	int  phy_clk_num;
-> >>>=20
+> >>> 
 > >>>   	void (*phy_init)(struct sun8i_hdmi_phy *phy);
 > >>>   	void (*phy_disable)(struct dw_hdmi *hdmi,
-> >>>   =09
+> >>>   	
 > >>>   			    struct sun8i_hdmi_phy *phy);
-> >>>=20
+> >>> 
 > >>> @@ -160,6 +161,7 @@ struct sun8i_hdmi_phy {
-> >>>=20
+> >>> 
 > >>>   	struct clk			*clk_mod;
 > >>>   	struct clk			*clk_phy;
 > >>>   	struct clk			*clk_pll0;
-> >>>=20
+> >>> 
 > >>> +	struct clk			*clk_pll1;
-> >>>=20
+> >>> 
 > >>>   	unsigned int			rcal;
 > >>>   	struct regmap			*regs;
 > >>>   	struct reset_control		*rst_phy;
-> >>>=20
+> >>> 
 > >>> @@ -188,6 +190,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi
 > >>> *hdmi);
-> >>>=20
+> >>> 
 > >>>   void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
 > >>>   const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
-> >>>=20
+> >>> 
 > >>> -int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device
 > >>> *dev);
 > >>> +int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device
 > >>> *dev,
 > >>> +			 int clk_num);
-> >>>=20
+> >>> 
 > >>>   #endif /* _SUN8I_DW_HDMI_H_ */
-> >>>=20
+> >>> 
 > >>> diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
 > >>> b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index
 > >>> 5a52fc489a9d..0eadf087fc46
 > >>> 100644
 > >>> --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
 > >>> +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-> >>> @@ -183,7 +183,13 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hd=
-mi
+> >>> @@ -183,7 +183,13 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi
 > >>> *hdmi,>
-> >>>=20
+> >>> 
 > >>>   	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
-> >>>   =09
+> >>>   	
 > >>>   			   SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
-> >>>=20
+> >>> 
 > >>> -	regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, pll_cfg1_init);
 > >>> +	/*
 > >>> +	 * NOTE: We have to be careful not to overwrite PHY parent
@@ -109,131 +107,126 @@ mi
 > >>> +	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
 > >>> +			   (u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
 > >>> +			   pll_cfg1_init);
-> >>>=20
+> >>> 
 > >>>   	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
-> >>>   =09
+> >>>   	
 > >>>   			   (u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
 > >>>   			   pll_cfg2_init);
-> >>>=20
+> >>> 
 > >>> @@ -232,7 +238,7 @@ static int sun8i_hdmi_phy_config(struct dw_hdmi
 > >>> *hdmi,
 > >>> void *data,>
-> >>>=20
+> >>> 
 > >>>   	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
-> >>>   =09
+> >>>   	
 > >>>   			   SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
-> >>>=20
+> >>> 
 > >>> -	if (phy->variant->has_phy_clk)
 > >>> +	if (phy->variant->phy_clk_num)
-> >>>=20
+> >>> 
 > >>>   		clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);
-> >>>   =09
-> >>>   	return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000=
-);
-> >>>=20
+> >>>   	
+> >>>   	return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000);
+> >>> 
 > >>> @@ -393,7 +399,7 @@ static const struct sun8i_hdmi_phy_variant
-> >>> sun8i_a83t_hdmi_phy =3D {>
-> >>>=20
+> >>> sun8i_a83t_hdmi_phy = {>
+> >>> 
 > >>>   };
-> >>>  =20
-> >>>   static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy =3D {
-> >>>=20
-> >>> -	.has_phy_clk =3D true,
-> >>> +	.phy_clk_num =3D 1,
-> >>>=20
-> >>>   	.phy_init =3D &sun8i_hdmi_phy_init_h3,
-> >>>   	.phy_disable =3D &sun8i_hdmi_phy_disable_h3,
-> >>>   	.phy_config =3D &sun8i_hdmi_phy_config_h3,
-> >>>=20
-> >>> @@ -464,7 +470,7 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hd=
-mi,
+> >>>   
+> >>>   static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
+> >>> 
+> >>> -	.has_phy_clk = true,
+> >>> +	.phy_clk_num = 1,
+> >>> 
+> >>>   	.phy_init = &sun8i_hdmi_phy_init_h3,
+> >>>   	.phy_disable = &sun8i_hdmi_phy_disable_h3,
+> >>>   	.phy_config = &sun8i_hdmi_phy_config_h3,
+> >>> 
+> >>> @@ -464,7 +470,7 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi,
 > >>> struct device_node *node)>
-> >>>=20
+> >>> 
 > >>>   		goto err_put_clk_bus;
-> >>>   =09
+> >>>   	
 > >>>   	}
-> >>>=20
+> >>> 
 > >>> -	if (phy->variant->has_phy_clk) {
 > >>> +	if (phy->variant->phy_clk_num) {
-> >>>=20
-> >>>   		phy->clk_pll0 =3D of_clk_get_by_name(node, "pll-0");
+> >>> 
+> >>>   		phy->clk_pll0 = of_clk_get_by_name(node, "pll-0");
 > >>>   		if (IS_ERR(phy->clk_pll0)) {
-> >>>   	=09
+> >>>   		
 > >>>   			dev_err(dev, "Could not get pll-0 clock\n");
-> >>>=20
+> >>> 
 > >>> @@ -472,7 +478,16 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi
 > >>> *hdmi,
 > >>> struct device_node *node)>
-> >>>=20
+> >>> 
 > >>>   			goto err_put_clk_mod;
-> >>>   	=09
+> >>>   		
 > >>>   		}
-> >>>=20
-> >>> -		ret =3D sun8i_phy_clk_create(phy, dev);
+> >>> 
+> >>> -		ret = sun8i_phy_clk_create(phy, dev);
 > >>> +		if (phy->variant->phy_clk_num) {
-> >>> +			phy->clk_pll1 =3D of_clk_get_by_name(node, "pll-1");
+> >>> +			phy->clk_pll1 = of_clk_get_by_name(node, "pll-1");
 > >>> +			if (IS_ERR(phy->clk_pll1)) {
 > >>> +				dev_err(dev, "Could not get pll-1 clock\n");
-> >>> +				ret =3D PTR_ERR(phy->clk_pll1);
+> >>> +				ret = PTR_ERR(phy->clk_pll1);
 > >>> +				goto err_put_clk_mod;
 > >>> +			}
 > >>> +		}
 > >>> +
-> >>=20
-> >> You have a bug here. If phy_clk_num =3D=3D 1, you'll still try to look=
-up
+> >> 
+> >> You have a bug here. If phy_clk_num == 1, you'll still try to lookup
 > >> pll-1.
-> >=20
+> > 
 > > This is actually WIP patch taken from my github. This issue was fixed
 > > already locally on disk. I thought Jagan will not use it until SRAM C
-> > patches land.>=20
-> >> And this is a bit sloppy, since if phy_clk_num =3D=3D 3, you won't try=
- to
+> > patches land.> 
+> >> And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
 > >> lookup pll-2 either.
-> >=20
+> > 
 > > It is highly unlikely this will be higher than 2, at least for this HDMI
 > > PHY, since it has only 1 bit reserved for parent selection. But since I
-> > have to fix it, I'll add ">=3D 2"
-> >=20
-> >>> +		ret =3D sun8i_phy_clk_create(phy, dev, phy->variant->phy_clk_num);
-> >>>=20
+> > have to fix it, I'll add ">= 2"
+> > 
+> >>> +		ret = sun8i_phy_clk_create(phy, dev, phy->variant->phy_clk_num);
+> >>> 
 > >>>   		if (ret) {
-> >>>   	=09
+> >>>   		
 > >>>   			dev_err(dev, "Couldn't create the PHY clock\n");
 > >>>   			goto err_put_clk_pll0;
-> >>>=20
-> >>> @@ -515,8 +530,8 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hd=
-mi,
+> >>> 
+> >>> @@ -515,8 +530,8 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi,
 > >>> struct device_node *node)>
-> >>>=20
+> >>> 
 > >>>   err_put_rst_phy:
 > >>>   	reset_control_put(phy->rst_phy);
-> >>>  =20
+> >>>   
 > >>>   err_put_clk_pll0:
 > >>> -	if (phy->variant->has_phy_clk)
 > >>> -		clk_put(phy->clk_pll0);
 > >>> +	clk_put(phy->clk_pll0);
 > >>> +	clk_put(phy->clk_pll1);
-> >>>=20
+> >>> 
 > >>>   err_put_clk_mod:
 > >>>   	clk_put(phy->clk_mod);
-> >>>  =20
+> >>>   
 > >>>   err_put_clk_bus:
 > >>> @@ -536,8 +551,8 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi
 > >>> *hdmi)
-> >>>=20
+> >>> 
 > >>>   	reset_control_put(phy->rst_phy);
-> >>>=20
+> >>> 
 > >>> -	if (phy->variant->has_phy_clk)
 > >>> -		clk_put(phy->clk_pll0);
 > >>> +	clk_put(phy->clk_pll0);
 > >>> +	clk_put(phy->clk_pll1);
-> >>>=20
+> >>> 
 > >>>   	clk_put(phy->clk_mod);
 > >>>   	clk_put(phy->clk_bus);
-> >>>  =20
+> >>>   
 > >>>   }
-> >>>=20
+> >>> 
 > >>> diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c
 > >>> b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c index
 > >>> faea449812f8..85b12fc96dbc 100644
@@ -242,84 +235,84 @@ mi,
 > >>> @@ -22,29 +22,36 @@ static int sun8i_phy_clk_determine_rate(struct
 > >>> clk_hw
 > >>> *hw,>
-> >>>=20
+> >>> 
 > >>>   {
-> >>>  =20
-> >>>   	unsigned long rate =3D req->rate;
-> >>>   	unsigned long best_rate =3D 0;
-> >>>=20
+> >>>   
+> >>>   	unsigned long rate = req->rate;
+> >>>   	unsigned long best_rate = 0;
+> >>> 
 > >>> -	struct clk_hw *parent;
-> >>> +	struct clk_hw *best_parent =3D NULL;
-> >>> +	struct clk_hw *parent =3D NULL;
-> >>>=20
-> >>>   	int best_div =3D 1;
-> >>>=20
+> >>> +	struct clk_hw *best_parent = NULL;
+> >>> +	struct clk_hw *parent = NULL;
+> >>> 
+> >>>   	int best_div = 1;
+> >>> 
 > >>> -	int i;
 > >>> +	int i, p;
-> >>>=20
-> >>> -	parent =3D clk_hw_get_parent(hw);
+> >>> 
+> >>> -	parent = clk_hw_get_parent(hw);
 > >>> -
-> >>> -	for (i =3D 1; i <=3D 16; i++) {
-> >>> -		unsigned long ideal =3D rate * i;
+> >>> -	for (i = 1; i <= 16; i++) {
+> >>> -		unsigned long ideal = rate * i;
 > >>> -		unsigned long rounded;
 > >>> -
-> >>> -		rounded =3D clk_hw_round_rate(parent, ideal);
+> >>> -		rounded = clk_hw_round_rate(parent, ideal);
 > >>> -
-> >>> -		if (rounded =3D=3D ideal) {
-> >>> -			best_rate =3D rounded;
-> >>> -			best_div =3D i;
+> >>> -		if (rounded == ideal) {
+> >>> -			best_rate = rounded;
+> >>> -			best_div = i;
 > >>> -			break;
 > >>> -		}
-> >>> +	for (p =3D 0; p < clk_hw_get_num_parents(hw); p++) {
-> >>> +		parent =3D clk_hw_get_parent_by_index(hw, p);
+> >>> +	for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
+> >>> +		parent = clk_hw_get_parent_by_index(hw, p);
 > >>> +		if (!parent)
 > >>> +			continue;
-> >>>=20
+> >>> 
 > >>> -		if (!best_rate ||
 > >>> -		    abs(rate - rounded / i) <
 > >>> -		    abs(rate - best_rate / best_div)) {
-> >>> -			best_rate =3D rounded;
-> >>> -			best_div =3D i;
-> >>> +		for (i =3D 1; i <=3D 16; i++) {
-> >>> +			unsigned long ideal =3D rate * i;
+> >>> -			best_rate = rounded;
+> >>> -			best_div = i;
+> >>> +		for (i = 1; i <= 16; i++) {
+> >>> +			unsigned long ideal = rate * i;
 > >>> +			unsigned long rounded;
 > >>> +
-> >>> +			rounded =3D clk_hw_round_rate(parent, ideal);
+> >>> +			rounded = clk_hw_round_rate(parent, ideal);
 > >>> +
-> >>> +			if (rounded =3D=3D ideal) {
-> >>> +				best_rate =3D rounded;
-> >>> +				best_div =3D i;
-> >>> +				best_parent =3D parent;
+> >>> +			if (rounded == ideal) {
+> >>> +				best_rate = rounded;
+> >>> +				best_div = i;
+> >>> +				best_parent = parent;
 > >>> +				break;
 > >>> +			}
 > >>> +
 > >>> +			if (!best_rate ||
 > >>> +			    abs(rate - rounded / i) <
 > >>> +			    abs(rate - best_rate / best_div)) {
-> >>> +				best_rate =3D rounded;
-> >>> +				best_div =3D i;
-> >>> +				best_parent =3D parent;
+> >>> +				best_rate = rounded;
+> >>> +				best_div = i;
+> >>> +				best_parent = parent;
 > >>> +			}
-> >>>=20
+> >>> 
 > >>>   		}
-> >>>   =09
+> >>>   	
 > >>>   	}
-> >>>=20
+> >>> 
 > >>> @@ -95,22 +102,58 @@ static int sun8i_phy_clk_set_rate(struct clk_hw
 > >>> *hw,
 > >>> unsigned long rate,>
-> >>>=20
+> >>> 
 > >>>   	return 0;
-> >>>  =20
+> >>>   
 > >>>   }
-> >>>=20
+> >>> 
 > >>> +static u8 sun8i_phy_clk_get_parent(struct clk_hw *hw)
 > >>> +{
-> >>> +	struct sun8i_phy_clk *priv =3D hw_to_phy_clk(hw);
+> >>> +	struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
 > >>> +	u32 reg;
 > >>> +
 > >>> +	regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, &reg);
-> >>> +	reg =3D (reg & SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK) >>
+> >>> +	reg = (reg & SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK) >>
 > >>> +	      SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT;
 > >>> +
 > >>> +	return reg;
@@ -327,7 +320,7 @@ mi,
 > >>> +
 > >>> +static int sun8i_phy_clk_set_parent(struct clk_hw *hw, u8 index)
 > >>> +{
-> >>> +	struct sun8i_phy_clk *priv =3D hw_to_phy_clk(hw);
+> >>> +	struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
 > >>> +
 > >>> +	if (index > 1)
 > >>> +		return -EINVAL;
@@ -339,44 +332,39 @@ mi,
 > >>> +	return 0;
 > >>> +}
 > >>> +
-> >>=20
+> >> 
 > >> The DT bindings changes and the clk changes should be part of separate
 > >> patches.
-> >=20
+> > 
 > > By DT bindings changes you mean code which reads DT and not DT
 > > documentation, right?
-> >=20
+> > 
 > > Ok, I'll split it.
-> >=20
-> > BTW, I'll resend fixed version of this patch for my R40 HDMI series, si=
-nce
+> > 
+> > BTW, I'll resend fixed version of this patch for my R40 HDMI series, since
 > > there is nothing to hold it back, unlike for this.
-> >=20
+> > 
 > > Best regards,
 > > Jernej
-> >=20
-> >=20
-> >=20
+> > 
+> > 
+> > 
 > > _______________________________________________
 > > linux-arm-kernel mailing list
-> > linux-arm-kernel@lists.infradead.org
+> > linux-arm-kernel at lists.infradead.org
 > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
->=20
+> 
 > you have been talking about SRAM patches, required for A64 DE2, for
 > about a half a year.
 > May I ask you to explain in a couple of words why they are so important ?
 > I am really curious because I have DE2 already working on my A64 without
 > those magic patches..
->=20
+> 
 
-You probably have HDMI enabled in U-Boot, right? If you disable that driver=
- in=20
-U-Boot, Linux driver shouldn't work anymore. There is consensus that Linux =
-A64=20
-DE2 driver shouldn't rely on U-Boot setting bits. Those SRAM C patches will=
-=20
-probably also affect how DT DE2 entries are written, especially if it will =
-be=20
+You probably have HDMI enabled in U-Boot, right? If you disable that driver in 
+U-Boot, Linux driver shouldn't work anymore. There is consensus that Linux A64 
+DE2 driver shouldn't rely on U-Boot setting bits. Those SRAM C patches will 
+probably also affect how DT DE2 entries are written, especially if it will be 
 implemented as a bus, as once proposed by Icenowy.
 
 Best regards,
diff --git a/a/content_digest b/N1/content_digest
index c8e2ca6..7801d26 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,133 +1,113 @@
  "ref\020180518094536.17201-1-jagan@amarulasolutions.com\0"
  "ref\04909574.Q3IFWM0xt6@jernej-laptop\0"
  "ref\0824c6989-7930-86dc-1195-494580f6cb38@orpaltech.com\0"
- "From\0Jernej \305\240krabec <jernej.skrabec@siol.net>\0"
- "Subject\0Re: [PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents\0"
+ "From\0jernej.skrabec@siol.net (Jernej \305\240krabec)\0"
+ "Subject\0[PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents\0"
  "Date\0Fri, 18 May 2018 17:15:44 +0200\0"
- "To\0Sergey Suloev <ssuloev@orpaltech.com>\0"
- "Cc\0Maxime Ripard <maxime.ripard@bootlin.com>"
-  Mark Rutland <mark.rutland@arm.com>
-  devicetree@vger.kernel.org
-  David Airlie <airlied@linux.ie>
-  Catalin Marinas <catalin.marinas@arm.com>
-  Michael Turquette <mturquette@baylibre.com>
-  linux-sunxi@googlegroups.com
-  Will Deacon <will.deacon@arm.com>
-  linux-kernel@vger.kernel.org
-  dri-devel@lists.freedesktop.org
-  Stephen Boyd <sboyd@kernel.org>
-  Chen-Yu Tsai <wens@csie.org>
-  Rob Herring <robh+dt@kernel.org>
-  Jagan Teki <jagan@amarulasolutions.com>
-  Michael Trimarchi <michael@amarulasolutions.com>
-  linux-clk@vger.kernel.org
-  linux-arm-kernel@lists.infradead.org
- " Icenowy Zheng <icenowy@aosc.io>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "Hi,\n"
  "\n"
  "Dne petek, 18. maj 2018 ob 17:09:40 CEST je Sergey Suloev napisal(a):\n"
  "> Hi, guys,\n"
- ">=20\n"
- "> On 05/18/2018 05:46 PM, Jernej =C5=A0krabec wrote:\n"
+ "> \n"
+ "> On 05/18/2018 05:46 PM, Jernej ?krabec wrote:\n"
  "> > Hi,\n"
- "> >=20\n"
+ "> > \n"
  "> > Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):\n"
  "> >> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:\n"
  "> >>> From: Jernej Skrabec <jernej.skrabec@siol.net>\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> Some SoCs with DW HDMI have multiple possible clock parents, like A64\n"
  "> >>> and R40.\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> Expand HDMI PHY clock driver to support second clock parent.\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>\n"
  "> >>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>\n"
  "> >>> ---\n"
  "> >>> Changes for v2:\n"
  "> >>> - new patch\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h      |  9 ++-\n"
  "> >>>   drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c     | 33 ++++++++---\n"
  "> >>>   drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 89\n"
  "> >>>   ++++++++++++++++++++++-------- 3 files changed, 96 insertions(+), 35\n"
  "> >>>   deletions(-)\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h\n"
- "> >>> b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 79154f0f674a..303189d66=\n"
- "02c\n"
+ "> >>> b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 79154f0f674a..303189d6602c\n"
  "> >>> 100644\n"
  "> >>> --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h\n"
  "> >>> +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h\n"
  "> >>> @@ -98,7 +98,8 @@\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN\t\tBIT(29)\n"
  "> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN\t\tBIT(28)\n"
  "> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33\tBIT(27)\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> -#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL\tBIT(26)\n"
  "> >>> +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK\tBIT(26)\n"
  "> >>> +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT\t26\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN\t\tBIT(25)\n"
  "> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x)\t((x) << 22)\n"
  "> >>>   #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x)\t((x) << 20)\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> @@ -146,7 +147,7 @@\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   struct sun8i_hdmi_phy;\n"
- "> >>>  =20\n"
+ "> >>>   \n"
  "> >>>   struct sun8i_hdmi_phy_variant {\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> -\tbool has_phy_clk;\n"
  "> >>> +\tint  phy_clk_num;\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \tvoid (*phy_init)(struct sun8i_hdmi_phy *phy);\n"
  "> >>>   \tvoid (*phy_disable)(struct dw_hdmi *hdmi,\n"
- "> >>>   =09\n"
+ "> >>>   \t\n"
  "> >>>   \t\t\t    struct sun8i_hdmi_phy *phy);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> @@ -160,6 +161,7 @@ struct sun8i_hdmi_phy {\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \tstruct clk\t\t\t*clk_mod;\n"
  "> >>>   \tstruct clk\t\t\t*clk_phy;\n"
  "> >>>   \tstruct clk\t\t\t*clk_pll0;\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> +\tstruct clk\t\t\t*clk_pll1;\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \tunsigned int\t\t\trcal;\n"
  "> >>>   \tstruct regmap\t\t\t*regs;\n"
  "> >>>   \tstruct reset_control\t\t*rst_phy;\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> @@ -188,6 +190,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi\n"
  "> >>> *hdmi);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);\n"
  "> >>>   const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> -int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device\n"
  "> >>> *dev);\n"
  "> >>> +int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device\n"
  "> >>> *dev,\n"
  "> >>> +\t\t\t int clk_num);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   #endif /* _SUN8I_DW_HDMI_H_ */\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c\n"
  "> >>> b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index\n"
  "> >>> 5a52fc489a9d..0eadf087fc46\n"
  "> >>> 100644\n"
  "> >>> --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c\n"
  "> >>> +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c\n"
- "> >>> @@ -183,7 +183,13 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hd=\n"
- "mi\n"
+ "> >>> @@ -183,7 +183,13 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi\n"
  "> >>> *hdmi,>\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \tregmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,\n"
- "> >>>   =09\n"
+ "> >>>   \t\n"
  "> >>>   \t\t\t   SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> -\tregmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, pll_cfg1_init);\n"
  "> >>> +\t/*\n"
  "> >>> +\t * NOTE: We have to be careful not to overwrite PHY parent\n"
@@ -136,131 +116,126 @@
  "> >>> +\tregmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,\n"
  "> >>> +\t\t\t   (u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,\n"
  "> >>> +\t\t\t   pll_cfg1_init);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \tregmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,\n"
- "> >>>   =09\n"
+ "> >>>   \t\n"
  "> >>>   \t\t\t   (u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,\n"
  "> >>>   \t\t\t   pll_cfg2_init);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> @@ -232,7 +238,7 @@ static int sun8i_hdmi_phy_config(struct dw_hdmi\n"
  "> >>> *hdmi,\n"
  "> >>> void *data,>\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \tregmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,\n"
- "> >>>   =09\n"
+ "> >>>   \t\n"
  "> >>>   \t\t\t   SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> -\tif (phy->variant->has_phy_clk)\n"
  "> >>> +\tif (phy->variant->phy_clk_num)\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \t\tclk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);\n"
- "> >>>   =09\n"
- "> >>>   \treturn phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000=\n"
- ");\n"
- "> >>>=20\n"
+ "> >>>   \t\n"
+ "> >>>   \treturn phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000);\n"
+ "> >>> \n"
  "> >>> @@ -393,7 +399,7 @@ static const struct sun8i_hdmi_phy_variant\n"
- "> >>> sun8i_a83t_hdmi_phy =3D {>\n"
- "> >>>=20\n"
+ "> >>> sun8i_a83t_hdmi_phy = {>\n"
+ "> >>> \n"
  "> >>>   };\n"
- "> >>>  =20\n"
- "> >>>   static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy =3D {\n"
- "> >>>=20\n"
- "> >>> -\t.has_phy_clk =3D true,\n"
- "> >>> +\t.phy_clk_num =3D 1,\n"
- "> >>>=20\n"
- "> >>>   \t.phy_init =3D &sun8i_hdmi_phy_init_h3,\n"
- "> >>>   \t.phy_disable =3D &sun8i_hdmi_phy_disable_h3,\n"
- "> >>>   \t.phy_config =3D &sun8i_hdmi_phy_config_h3,\n"
- "> >>>=20\n"
- "> >>> @@ -464,7 +470,7 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hd=\n"
- "mi,\n"
+ "> >>>   \n"
+ "> >>>   static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {\n"
+ "> >>> \n"
+ "> >>> -\t.has_phy_clk = true,\n"
+ "> >>> +\t.phy_clk_num = 1,\n"
+ "> >>> \n"
+ "> >>>   \t.phy_init = &sun8i_hdmi_phy_init_h3,\n"
+ "> >>>   \t.phy_disable = &sun8i_hdmi_phy_disable_h3,\n"
+ "> >>>   \t.phy_config = &sun8i_hdmi_phy_config_h3,\n"
+ "> >>> \n"
+ "> >>> @@ -464,7 +470,7 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi,\n"
  "> >>> struct device_node *node)>\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \t\tgoto err_put_clk_bus;\n"
- "> >>>   =09\n"
+ "> >>>   \t\n"
  "> >>>   \t}\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> -\tif (phy->variant->has_phy_clk) {\n"
  "> >>> +\tif (phy->variant->phy_clk_num) {\n"
- "> >>>=20\n"
- "> >>>   \t\tphy->clk_pll0 =3D of_clk_get_by_name(node, \"pll-0\");\n"
+ "> >>> \n"
+ "> >>>   \t\tphy->clk_pll0 = of_clk_get_by_name(node, \"pll-0\");\n"
  "> >>>   \t\tif (IS_ERR(phy->clk_pll0)) {\n"
- "> >>>   \t=09\n"
+ "> >>>   \t\t\n"
  "> >>>   \t\t\tdev_err(dev, \"Could not get pll-0 clock\\n\");\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> @@ -472,7 +478,16 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi\n"
  "> >>> *hdmi,\n"
  "> >>> struct device_node *node)>\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \t\t\tgoto err_put_clk_mod;\n"
- "> >>>   \t=09\n"
+ "> >>>   \t\t\n"
  "> >>>   \t\t}\n"
- "> >>>=20\n"
- "> >>> -\t\tret =3D sun8i_phy_clk_create(phy, dev);\n"
+ "> >>> \n"
+ "> >>> -\t\tret = sun8i_phy_clk_create(phy, dev);\n"
  "> >>> +\t\tif (phy->variant->phy_clk_num) {\n"
- "> >>> +\t\t\tphy->clk_pll1 =3D of_clk_get_by_name(node, \"pll-1\");\n"
+ "> >>> +\t\t\tphy->clk_pll1 = of_clk_get_by_name(node, \"pll-1\");\n"
  "> >>> +\t\t\tif (IS_ERR(phy->clk_pll1)) {\n"
  "> >>> +\t\t\t\tdev_err(dev, \"Could not get pll-1 clock\\n\");\n"
- "> >>> +\t\t\t\tret =3D PTR_ERR(phy->clk_pll1);\n"
+ "> >>> +\t\t\t\tret = PTR_ERR(phy->clk_pll1);\n"
  "> >>> +\t\t\t\tgoto err_put_clk_mod;\n"
  "> >>> +\t\t\t}\n"
  "> >>> +\t\t}\n"
  "> >>> +\n"
- "> >>=20\n"
- "> >> You have a bug here. If phy_clk_num =3D=3D 1, you'll still try to look=\n"
- "up\n"
+ "> >> \n"
+ "> >> You have a bug here. If phy_clk_num == 1, you'll still try to lookup\n"
  "> >> pll-1.\n"
- "> >=20\n"
+ "> > \n"
  "> > This is actually WIP patch taken from my github. This issue was fixed\n"
  "> > already locally on disk. I thought Jagan will not use it until SRAM C\n"
- "> > patches land.>=20\n"
- "> >> And this is a bit sloppy, since if phy_clk_num =3D=3D 3, you won't try=\n"
- " to\n"
+ "> > patches land.> \n"
+ "> >> And this is a bit sloppy, since if phy_clk_num == 3, you won't try to\n"
  "> >> lookup pll-2 either.\n"
- "> >=20\n"
+ "> > \n"
  "> > It is highly unlikely this will be higher than 2, at least for this HDMI\n"
  "> > PHY, since it has only 1 bit reserved for parent selection. But since I\n"
- "> > have to fix it, I'll add \">=3D 2\"\n"
- "> >=20\n"
- "> >>> +\t\tret =3D sun8i_phy_clk_create(phy, dev, phy->variant->phy_clk_num);\n"
- "> >>>=20\n"
+ "> > have to fix it, I'll add \">= 2\"\n"
+ "> > \n"
+ "> >>> +\t\tret = sun8i_phy_clk_create(phy, dev, phy->variant->phy_clk_num);\n"
+ "> >>> \n"
  "> >>>   \t\tif (ret) {\n"
- "> >>>   \t=09\n"
+ "> >>>   \t\t\n"
  "> >>>   \t\t\tdev_err(dev, \"Couldn't create the PHY clock\\n\");\n"
  "> >>>   \t\t\tgoto err_put_clk_pll0;\n"
- "> >>>=20\n"
- "> >>> @@ -515,8 +530,8 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hd=\n"
- "mi,\n"
+ "> >>> \n"
+ "> >>> @@ -515,8 +530,8 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi,\n"
  "> >>> struct device_node *node)>\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   err_put_rst_phy:\n"
  "> >>>   \treset_control_put(phy->rst_phy);\n"
- "> >>>  =20\n"
+ "> >>>   \n"
  "> >>>   err_put_clk_pll0:\n"
  "> >>> -\tif (phy->variant->has_phy_clk)\n"
  "> >>> -\t\tclk_put(phy->clk_pll0);\n"
  "> >>> +\tclk_put(phy->clk_pll0);\n"
  "> >>> +\tclk_put(phy->clk_pll1);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   err_put_clk_mod:\n"
  "> >>>   \tclk_put(phy->clk_mod);\n"
- "> >>>  =20\n"
+ "> >>>   \n"
  "> >>>   err_put_clk_bus:\n"
  "> >>> @@ -536,8 +551,8 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi\n"
  "> >>> *hdmi)\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \treset_control_put(phy->rst_phy);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> -\tif (phy->variant->has_phy_clk)\n"
  "> >>> -\t\tclk_put(phy->clk_pll0);\n"
  "> >>> +\tclk_put(phy->clk_pll0);\n"
  "> >>> +\tclk_put(phy->clk_pll1);\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \tclk_put(phy->clk_mod);\n"
  "> >>>   \tclk_put(phy->clk_bus);\n"
- "> >>>  =20\n"
+ "> >>>   \n"
  "> >>>   }\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c\n"
  "> >>> b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c index\n"
  "> >>> faea449812f8..85b12fc96dbc 100644\n"
@@ -269,84 +244,84 @@
  "> >>> @@ -22,29 +22,36 @@ static int sun8i_phy_clk_determine_rate(struct\n"
  "> >>> clk_hw\n"
  "> >>> *hw,>\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   {\n"
- "> >>>  =20\n"
- "> >>>   \tunsigned long rate =3D req->rate;\n"
- "> >>>   \tunsigned long best_rate =3D 0;\n"
- "> >>>=20\n"
+ "> >>>   \n"
+ "> >>>   \tunsigned long rate = req->rate;\n"
+ "> >>>   \tunsigned long best_rate = 0;\n"
+ "> >>> \n"
  "> >>> -\tstruct clk_hw *parent;\n"
- "> >>> +\tstruct clk_hw *best_parent =3D NULL;\n"
- "> >>> +\tstruct clk_hw *parent =3D NULL;\n"
- "> >>>=20\n"
- "> >>>   \tint best_div =3D 1;\n"
- "> >>>=20\n"
+ "> >>> +\tstruct clk_hw *best_parent = NULL;\n"
+ "> >>> +\tstruct clk_hw *parent = NULL;\n"
+ "> >>> \n"
+ "> >>>   \tint best_div = 1;\n"
+ "> >>> \n"
  "> >>> -\tint i;\n"
  "> >>> +\tint i, p;\n"
- "> >>>=20\n"
- "> >>> -\tparent =3D clk_hw_get_parent(hw);\n"
+ "> >>> \n"
+ "> >>> -\tparent = clk_hw_get_parent(hw);\n"
  "> >>> -\n"
- "> >>> -\tfor (i =3D 1; i <=3D 16; i++) {\n"
- "> >>> -\t\tunsigned long ideal =3D rate * i;\n"
+ "> >>> -\tfor (i = 1; i <= 16; i++) {\n"
+ "> >>> -\t\tunsigned long ideal = rate * i;\n"
  "> >>> -\t\tunsigned long rounded;\n"
  "> >>> -\n"
- "> >>> -\t\trounded =3D clk_hw_round_rate(parent, ideal);\n"
+ "> >>> -\t\trounded = clk_hw_round_rate(parent, ideal);\n"
  "> >>> -\n"
- "> >>> -\t\tif (rounded =3D=3D ideal) {\n"
- "> >>> -\t\t\tbest_rate =3D rounded;\n"
- "> >>> -\t\t\tbest_div =3D i;\n"
+ "> >>> -\t\tif (rounded == ideal) {\n"
+ "> >>> -\t\t\tbest_rate = rounded;\n"
+ "> >>> -\t\t\tbest_div = i;\n"
  "> >>> -\t\t\tbreak;\n"
  "> >>> -\t\t}\n"
- "> >>> +\tfor (p =3D 0; p < clk_hw_get_num_parents(hw); p++) {\n"
- "> >>> +\t\tparent =3D clk_hw_get_parent_by_index(hw, p);\n"
+ "> >>> +\tfor (p = 0; p < clk_hw_get_num_parents(hw); p++) {\n"
+ "> >>> +\t\tparent = clk_hw_get_parent_by_index(hw, p);\n"
  "> >>> +\t\tif (!parent)\n"
  "> >>> +\t\t\tcontinue;\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> -\t\tif (!best_rate ||\n"
  "> >>> -\t\t    abs(rate - rounded / i) <\n"
  "> >>> -\t\t    abs(rate - best_rate / best_div)) {\n"
- "> >>> -\t\t\tbest_rate =3D rounded;\n"
- "> >>> -\t\t\tbest_div =3D i;\n"
- "> >>> +\t\tfor (i =3D 1; i <=3D 16; i++) {\n"
- "> >>> +\t\t\tunsigned long ideal =3D rate * i;\n"
+ "> >>> -\t\t\tbest_rate = rounded;\n"
+ "> >>> -\t\t\tbest_div = i;\n"
+ "> >>> +\t\tfor (i = 1; i <= 16; i++) {\n"
+ "> >>> +\t\t\tunsigned long ideal = rate * i;\n"
  "> >>> +\t\t\tunsigned long rounded;\n"
  "> >>> +\n"
- "> >>> +\t\t\trounded =3D clk_hw_round_rate(parent, ideal);\n"
+ "> >>> +\t\t\trounded = clk_hw_round_rate(parent, ideal);\n"
  "> >>> +\n"
- "> >>> +\t\t\tif (rounded =3D=3D ideal) {\n"
- "> >>> +\t\t\t\tbest_rate =3D rounded;\n"
- "> >>> +\t\t\t\tbest_div =3D i;\n"
- "> >>> +\t\t\t\tbest_parent =3D parent;\n"
+ "> >>> +\t\t\tif (rounded == ideal) {\n"
+ "> >>> +\t\t\t\tbest_rate = rounded;\n"
+ "> >>> +\t\t\t\tbest_div = i;\n"
+ "> >>> +\t\t\t\tbest_parent = parent;\n"
  "> >>> +\t\t\t\tbreak;\n"
  "> >>> +\t\t\t}\n"
  "> >>> +\n"
  "> >>> +\t\t\tif (!best_rate ||\n"
  "> >>> +\t\t\t    abs(rate - rounded / i) <\n"
  "> >>> +\t\t\t    abs(rate - best_rate / best_div)) {\n"
- "> >>> +\t\t\t\tbest_rate =3D rounded;\n"
- "> >>> +\t\t\t\tbest_div =3D i;\n"
- "> >>> +\t\t\t\tbest_parent =3D parent;\n"
+ "> >>> +\t\t\t\tbest_rate = rounded;\n"
+ "> >>> +\t\t\t\tbest_div = i;\n"
+ "> >>> +\t\t\t\tbest_parent = parent;\n"
  "> >>> +\t\t\t}\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \t\t}\n"
- "> >>>   =09\n"
+ "> >>>   \t\n"
  "> >>>   \t}\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> @@ -95,22 +102,58 @@ static int sun8i_phy_clk_set_rate(struct clk_hw\n"
  "> >>> *hw,\n"
  "> >>> unsigned long rate,>\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>>   \treturn 0;\n"
- "> >>>  =20\n"
+ "> >>>   \n"
  "> >>>   }\n"
- "> >>>=20\n"
+ "> >>> \n"
  "> >>> +static u8 sun8i_phy_clk_get_parent(struct clk_hw *hw)\n"
  "> >>> +{\n"
- "> >>> +\tstruct sun8i_phy_clk *priv =3D hw_to_phy_clk(hw);\n"
+ "> >>> +\tstruct sun8i_phy_clk *priv = hw_to_phy_clk(hw);\n"
  "> >>> +\tu32 reg;\n"
  "> >>> +\n"
  "> >>> +\tregmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, &reg);\n"
- "> >>> +\treg =3D (reg & SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK) >>\n"
+ "> >>> +\treg = (reg & SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK) >>\n"
  "> >>> +\t      SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT;\n"
  "> >>> +\n"
  "> >>> +\treturn reg;\n"
@@ -354,7 +329,7 @@
  "> >>> +\n"
  "> >>> +static int sun8i_phy_clk_set_parent(struct clk_hw *hw, u8 index)\n"
  "> >>> +{\n"
- "> >>> +\tstruct sun8i_phy_clk *priv =3D hw_to_phy_clk(hw);\n"
+ "> >>> +\tstruct sun8i_phy_clk *priv = hw_to_phy_clk(hw);\n"
  "> >>> +\n"
  "> >>> +\tif (index > 1)\n"
  "> >>> +\t\treturn -EINVAL;\n"
@@ -366,47 +341,42 @@
  "> >>> +\treturn 0;\n"
  "> >>> +}\n"
  "> >>> +\n"
- "> >>=20\n"
+ "> >> \n"
  "> >> The DT bindings changes and the clk changes should be part of separate\n"
  "> >> patches.\n"
- "> >=20\n"
+ "> > \n"
  "> > By DT bindings changes you mean code which reads DT and not DT\n"
  "> > documentation, right?\n"
- "> >=20\n"
+ "> > \n"
  "> > Ok, I'll split it.\n"
- "> >=20\n"
- "> > BTW, I'll resend fixed version of this patch for my R40 HDMI series, si=\n"
- "nce\n"
+ "> > \n"
+ "> > BTW, I'll resend fixed version of this patch for my R40 HDMI series, since\n"
  "> > there is nothing to hold it back, unlike for this.\n"
- "> >=20\n"
+ "> > \n"
  "> > Best regards,\n"
  "> > Jernej\n"
- "> >=20\n"
- "> >=20\n"
- "> >=20\n"
+ "> > \n"
+ "> > \n"
+ "> > \n"
  "> > _______________________________________________\n"
  "> > linux-arm-kernel mailing list\n"
- "> > linux-arm-kernel@lists.infradead.org\n"
+ "> > linux-arm-kernel at lists.infradead.org\n"
  "> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel\n"
- ">=20\n"
+ "> \n"
  "> you have been talking about SRAM patches, required for A64 DE2, for\n"
  "> about a half a year.\n"
  "> May I ask you to explain in a couple of words why they are so important ?\n"
  "> I am really curious because I have DE2 already working on my A64 without\n"
  "> those magic patches..\n"
- ">=20\n"
+ "> \n"
  "\n"
- "You probably have HDMI enabled in U-Boot, right? If you disable that driver=\n"
- " in=20\n"
- "U-Boot, Linux driver shouldn't work anymore. There is consensus that Linux =\n"
- "A64=20\n"
- "DE2 driver shouldn't rely on U-Boot setting bits. Those SRAM C patches will=\n"
- "=20\n"
- "probably also affect how DT DE2 entries are written, especially if it will =\n"
- "be=20\n"
+ "You probably have HDMI enabled in U-Boot, right? If you disable that driver in \n"
+ "U-Boot, Linux driver shouldn't work anymore. There is consensus that Linux A64 \n"
+ "DE2 driver shouldn't rely on U-Boot setting bits. Those SRAM C patches will \n"
+ "probably also affect how DT DE2 entries are written, especially if it will be \n"
  "implemented as a bus, as once proposed by Icenowy.\n"
  "\n"
  "Best regards,\n"
  Jernej
 
-1139f6316a47865455f924585fe927eaa0a91ed824deb4a8e223fee0eae5f299
+64136dabdab332d756fb602a46fed4496d38d33873f8e33dfd607cb9c4360ba9
