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[201.69.66.110]) by smtp.gmail.com with ESMTPSA id w18-20020a056870a2d200b001aa1779d0besm7581043oak.7.2023.06.29.05.34.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Jun 2023 05:34:42 -0700 (PDT) Message-ID: <317de214-2fb9-ca55-d3f0-b630a13c1933@ventanamicro.com> Date: Thu, 29 Jun 2023 09:34:36 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v5 1/1] target/riscv: Add RVV registers to log Content-Language: en-US To: Ivan Klokov , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com References: <20230629083730.386604-1-ivan.klokov@syntacore.com> From: Daniel Henrique Barboza In-Reply-To: <20230629083730.386604-1-ivan.klokov@syntacore.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.093, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 6/29/23 05:37, Ivan Klokov wrote: > Print RvV extension register to log if VPU option is enabled. > > Signed-off-by: Ivan Klokov > --- > v5: > - Fix typo, move macros out of function, direct access to cfg.vlen field. > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 56 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 881bddf393..ff29573b1f 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -55,6 +55,17 @@ struct isa_ext_data { > #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ > {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} > > +/* > + * From vector_helper.c > + * Note that vector data is stored in host-endian 64-bit chunks, > + * so addressing bytes needs a host-endian fixup. > + */ > +#if HOST_BIG_ENDIAN > +#define BYTE(x) ((x) ^ 7) > +#else > +#define BYTE(x) (x) > +#endif > + > /* > * Here are the ordering rules of extension naming defined by RISC-V > * specification : > @@ -183,6 +194,14 @@ const char * const riscv_fpr_regnames[] = { > "f30/ft10", "f31/ft11" > }; > > +const char * const riscv_rvv_regnames[] = { > + "v0", "v1", "v2", "v3", "v4", "v5", "v6", > + "v7", "v8", "v9", "v10", "v11", "v12", "v13", > + "v14", "v15", "v16", "v17", "v18", "v19", "v20", > + "v21", "v22", "v23", "v24", "v25", "v26", "v27", > + "v28", "v29", "v30", "v31" > +}; > + > static const char * const riscv_excp_names[] = { > "misaligned_fetch", > "fault_fetch", > @@ -608,7 +627,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > { > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > - int i; > + int i, j; > + uint8_t *p; > > #if !defined(CONFIG_USER_ONLY) > if (riscv_has_ext(env, RVH)) { > @@ -692,6 +712,41 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > } > } > } > + if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { > + static const int dump_rvv_csrs[] = { > + CSR_VSTART, > + CSR_VXSAT, > + CSR_VXRM, > + CSR_VCSR, > + CSR_VL, > + CSR_VTYPE, > + CSR_VLENB, > + }; > + for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { > + int csrno = dump_rvv_csrs[i]; > + target_ulong val = 0; > + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); > + > + /* > + * Rely on the smode, hmode, etc, predicates within csr.c > + * to do the filtering of the registers that are present. > + */ > + if (res == RISCV_EXCP_NONE) { > + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", > + csr_ops[csrno].name, val); > + } > + } > + uint16_t vlenb = cpu->cfg.vlen >> 3; > + > + for (i = 0; i < 32; i++) { > + qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); > + p = (uint8_t *)env->vreg; > + for (j = vlenb - 1 ; j >= 0; j--) { > + qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j))); > + } > + qemu_fprintf(f, "\n"); > + } > + } > } > > static void riscv_cpu_set_pc(CPUState *cs, vaddr value)