Re: [RFC PATCH 09/11] sdhci: dt-bindings: configuration settings

[Krzysztof Kozlowski <krzk@kernel.org>]

On 07/05/2024 00:51, Krishna Yarlagadda wrote:
> SDHCI vendor tuning registers are configured using config setting
> framework. Document available config for Tegra SDHCI controllers.
> 
> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> ---
>  .../bindings/mmc/nvidia,tegra20-sdhci.yaml    | 36 +++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
> index 72987f0326a1..002bc1ffc156 100644
> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
> @@ -177,6 +177,37 @@ properties:
>        operates at a 1.8 V fixed I/O voltage.
>      $ref: /schemas/types.yaml#/definitions/flag
>  
> +  config:

No. This node does not re


> +    description: Config settings for SDHCI devices.
> +      Config setting is the configuration based on chip/board/system
> +      characterization on interface/controller settings. This is needed for
> +      - making the controller internal configuration to better perform
> +      - making the interface to work proper by setting drive strength, slew
> +        rates etc
> +      - making the low power leakage.
> +      SDHCI has configuration based on device speed modes.
> +      - common is set on all speeds and can be overridden by speed mode.
> +      - List of speed modes and their config name
> +        "default", /* MMC_TIMING_LEGACY */
> +        "sd-mmc-highspeed", /* MMC_TIMING_MMC_HS */
> +        "sd-mmc-highspeed", /* MMC_TIMING_SD_HS */
> +        "uhs-sdr12", /* MMC_TIMING_UHS_SDR12 */
> +        "uhs-sdr25", /* MMC_TIMING_UHS_SDR25 */
> +        "uhs-sdr50", /* MMC_TIMING_UHS_SDR50 */
> +        "uhs-sdr104", /* MMC_TIMING_UHS_SDR104 */
> +        "uhs-ddr52", /* MMC_TIMING_UHS_DDR50 */
> +        "uhs-ddr52", /* MMC_TIMING_MMC_DDR52 */
> +        "mmc-hs200", /* MMC_TIMING_MMC_HS200 */
> +        "mmc-hs400", /* MMC_TIMING_MMC_HS400 */
> +    type: object
> +    unevaluatedProperties: true

NAK.

> +    properties:
> +      nvidia,num-tuning-iter:
> +        description: Specify DQS trim value for HS400 timing.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 0xffff

"iterations" is decimal value. How it can be 0? 0 tries to time?


Best regards,
Krzysztof