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X-IronPort-AV: E=Sophos;i="5.97,261,1669071600"; d="scan'208";a="28776002" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 31 Jan 2023 15:55:17 +0100 Received: from steina-w.localnet (unknown [10.123.53.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 9AECF280056; Tue, 31 Jan 2023 15:55:17 +0100 (CET) From: Alexander Stein To: Marcel Ziswiler Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, Liu Ying , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Joakim Zhang , Marcel Ziswiler , Fabio Estevam , Frank Li , Krzysztof Kozlowski , Max Krummenacher , Peng Fan , Pengutronix Kernel Team , Philippe Schenker , Rob Herring , Sascha Hauer , Shawn Guo Subject: Re: [PATCH v5 05/10] arm64: dts: imx8qxp: add flexcan in adma Date: Tue, 31 Jan 2023 15:55:14 +0100 Message-ID: <3220805.aeNJFYEL58@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20230126110833.264439-6-marcel@ziswiler.com> References: <20230126110833.264439-1-marcel@ziswiler.com> <20230126110833.264439-6-marcel@ziswiler.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230131_065521_110938_097996C2 X-CRM114-Status: GOOD ( 20.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marcel, Am Donnerstag, 26. Januar 2023, 12:08:28 CET schrieb Marcel Ziswiler: > From: Joakim Zhang > > Add FlexCAN decive in adma subsystem. > > Signed-off-by: Joakim Zhang > Signed-off-by: Marcel Ziswiler On TQMa8XQP (i.MX8QXP) using flexcan1 and flexcan2: Tested-by: Alexander Stein Best regards, Alexander > --- > > (no changes since v4) > > Changes in v4: > - New patch combining the following downstream patches: > commit e8fe3f57223a ("arm64: dts: imx8qxp: add FlexCAN in adma") > commit 4e90361f1ed3 ("arm64: dts: imx8qxp: add multi-pd support for > CAN1/2") commit 899f516e61f8 ("arm64: dts: imx8: dma: fully switched to new > clk binding") commit 8a28ca15a058 ("arm64: dts: imx8qxp: drop multi-pd for > CAN device") commit c493402197dd ("arm64: dts: imx8: update CAN > fsl,clk-source and fsl,scu-index property") > > .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 72 +++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi > b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index > 6ccf926b77a5..2dce8f2ee3ea 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi > @@ -298,6 +298,65 @@ adc1: adc@5a890000 { > status = "disabled"; > }; > > + flexcan1: can@5a8d0000 { > + compatible = "fsl,imx8qm-flexcan"; > + reg = <0x5a8d0000 0x10000>; > + interrupts = ; > + interrupt-parent = <&gic>; > + clocks = <&can0_lpcg 1>, > + <&can0_lpcg 0>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates = <40000000>; > + power-domains = <&pd IMX_SC_R_CAN_0>; > + /* SLSlice[4] */ > + fsl,clk-source = /bits/ 8 <0>; > + fsl,scu-index = /bits/ 8 <0>; > + status = "disabled"; > + }; > + > + flexcan2: can@5a8e0000 { > + compatible = "fsl,imx8qm-flexcan"; > + reg = <0x5a8e0000 0x10000>; > + interrupts = ; > + interrupt-parent = <&gic>; > + /* CAN0 clock and PD is shared among all CAN instances as > + * CAN1 shares CAN0's clock and to enable CAN0's clock it > + * has to be powered on. > + */ > + clocks = <&can0_lpcg 1>, > + <&can0_lpcg 0>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates = <40000000>; > + power-domains = <&pd IMX_SC_R_CAN_1>; > + /* SLSlice[4] */ > + fsl,clk-source = /bits/ 8 <0>; > + fsl,scu-index = /bits/ 8 <1>; > + status = "disabled"; > + }; > + > + flexcan3: can@5a8f0000 { > + compatible = "fsl,imx8qm-flexcan"; > + reg = <0x5a8f0000 0x10000>; > + interrupts = ; > + interrupt-parent = <&gic>; > + /* CAN0 clock and PD is shared among all CAN instances as > + * CAN2 shares CAN0's clock and to enable CAN0's clock it > + * has to be powered on. > + */ > + clocks = <&can0_lpcg 1>, > + <&can0_lpcg 0>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates = <40000000>; > + power-domains = <&pd IMX_SC_R_CAN_2>; > + /* SLSlice[4] */ > + fsl,clk-source = /bits/ 8 <0>; > + fsl,scu-index = /bits/ 8 <2>; > + status = "disabled"; > + }; > + > i2c0_lpcg: clock-controller@5ac00000 { > compatible = "fsl,imx8qxp-lpcg"; > reg = <0x5ac00000 0x10000>; > @@ -369,4 +428,17 @@ adc1_lpcg: clock-controller@5ac90000 { > "adc1_lpcg_ipg_clk"; > power-domains = <&pd IMX_SC_R_ADC_1>; > }; > + > + can0_lpcg: clock-controller@5acd0000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x5acd0000 0x10000>; > + #clock-cells = <1>; > + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, > + <&dma_ipg_clk>, <&dma_ipg_clk>; > + clock-indices = , , ; > + clock-output-names = "can0_lpcg_pe_clk", > + "can0_lpcg_ipg_clk", > + "can0_lpcg_chi_clk"; > + power-domains = <&pd IMX_SC_R_CAN_0>; > + }; > }; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 821E6C38142 for ; Tue, 31 Jan 2023 14:55:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230329AbjAaOzZ (ORCPT ); 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X-IronPort-AV: E=Sophos;i="5.97,261,1669071600"; d="scan'208";a="28776002" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 31 Jan 2023 15:55:17 +0100 Received: from steina-w.localnet (unknown [10.123.53.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 9AECF280056; Tue, 31 Jan 2023 15:55:17 +0100 (CET) From: Alexander Stein To: Marcel Ziswiler Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, Liu Ying , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Joakim Zhang , Marcel Ziswiler , Fabio Estevam , Frank Li , Krzysztof Kozlowski , Max Krummenacher , Peng Fan , Pengutronix Kernel Team , Philippe Schenker , Rob Herring , Sascha Hauer , Shawn Guo Subject: Re: [PATCH v5 05/10] arm64: dts: imx8qxp: add flexcan in adma Date: Tue, 31 Jan 2023 15:55:14 +0100 Message-ID: <3220805.aeNJFYEL58@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20230126110833.264439-6-marcel@ziswiler.com> References: <20230126110833.264439-1-marcel@ziswiler.com> <20230126110833.264439-6-marcel@ziswiler.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Marcel, Am Donnerstag, 26. Januar 2023, 12:08:28 CET schrieb Marcel Ziswiler: > From: Joakim Zhang > > Add FlexCAN decive in adma subsystem. > > Signed-off-by: Joakim Zhang > Signed-off-by: Marcel Ziswiler On TQMa8XQP (i.MX8QXP) using flexcan1 and flexcan2: Tested-by: Alexander Stein Best regards, Alexander > --- > > (no changes since v4) > > Changes in v4: > - New patch combining the following downstream patches: > commit e8fe3f57223a ("arm64: dts: imx8qxp: add FlexCAN in adma") > commit 4e90361f1ed3 ("arm64: dts: imx8qxp: add multi-pd support for > CAN1/2") commit 899f516e61f8 ("arm64: dts: imx8: dma: fully switched to new > clk binding") commit 8a28ca15a058 ("arm64: dts: imx8qxp: drop multi-pd for > CAN device") commit c493402197dd ("arm64: dts: imx8: update CAN > fsl,clk-source and fsl,scu-index property") > > .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 72 +++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi > b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index > 6ccf926b77a5..2dce8f2ee3ea 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi > @@ -298,6 +298,65 @@ adc1: adc@5a890000 { > status = "disabled"; > }; > > + flexcan1: can@5a8d0000 { > + compatible = "fsl,imx8qm-flexcan"; > + reg = <0x5a8d0000 0x10000>; > + interrupts = ; > + interrupt-parent = <&gic>; > + clocks = <&can0_lpcg 1>, > + <&can0_lpcg 0>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates = <40000000>; > + power-domains = <&pd IMX_SC_R_CAN_0>; > + /* SLSlice[4] */ > + fsl,clk-source = /bits/ 8 <0>; > + fsl,scu-index = /bits/ 8 <0>; > + status = "disabled"; > + }; > + > + flexcan2: can@5a8e0000 { > + compatible = "fsl,imx8qm-flexcan"; > + reg = <0x5a8e0000 0x10000>; > + interrupts = ; > + interrupt-parent = <&gic>; > + /* CAN0 clock and PD is shared among all CAN instances as > + * CAN1 shares CAN0's clock and to enable CAN0's clock it > + * has to be powered on. > + */ > + clocks = <&can0_lpcg 1>, > + <&can0_lpcg 0>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates = <40000000>; > + power-domains = <&pd IMX_SC_R_CAN_1>; > + /* SLSlice[4] */ > + fsl,clk-source = /bits/ 8 <0>; > + fsl,scu-index = /bits/ 8 <1>; > + status = "disabled"; > + }; > + > + flexcan3: can@5a8f0000 { > + compatible = "fsl,imx8qm-flexcan"; > + reg = <0x5a8f0000 0x10000>; > + interrupts = ; > + interrupt-parent = <&gic>; > + /* CAN0 clock and PD is shared among all CAN instances as > + * CAN2 shares CAN0's clock and to enable CAN0's clock it > + * has to be powered on. > + */ > + clocks = <&can0_lpcg 1>, > + <&can0_lpcg 0>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates = <40000000>; > + power-domains = <&pd IMX_SC_R_CAN_2>; > + /* SLSlice[4] */ > + fsl,clk-source = /bits/ 8 <0>; > + fsl,scu-index = /bits/ 8 <2>; > + status = "disabled"; > + }; > + > i2c0_lpcg: clock-controller@5ac00000 { > compatible = "fsl,imx8qxp-lpcg"; > reg = <0x5ac00000 0x10000>; > @@ -369,4 +428,17 @@ adc1_lpcg: clock-controller@5ac90000 { > "adc1_lpcg_ipg_clk"; > power-domains = <&pd IMX_SC_R_ADC_1>; > }; > + > + can0_lpcg: clock-controller@5acd0000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x5acd0000 0x10000>; > + #clock-cells = <1>; > + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, > + <&dma_ipg_clk>, <&dma_ipg_clk>; > + clock-indices = , , ; > + clock-output-names = "can0_lpcg_pe_clk", > + "can0_lpcg_ipg_clk", > + "can0_lpcg_chi_clk"; > + power-domains = <&pd IMX_SC_R_CAN_0>; > + }; > };