From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Laurent Pinchart To: Kieran Bingham Cc: Kieran Bingham , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Simon Horman , geert@glider.be, Kieran Bingham , David Airlie , Rob Herring , Mark Rutland , Laurent Pinchart , "open list:DRM DRIVERS" , open list Subject: Re: [PATCH 3/8] dt-bindings: display: renesas,lvds: Add LVDS binding for D3 Date: Thu, 15 Feb 2018 16:04:55 +0200 Message-ID: <3242490.rUUU4MHlpR@avalon> In-Reply-To: References: <1518683903-10681-1-git-send-email-kbingham@kernel.org> <1518683903-10681-4-git-send-email-kbingham@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: devicetree-owner@vger.kernel.org List-ID: Hi Kieran, On Thursday, 15 February 2018 10:45:33 EET Kieran Bingham wrote: > On 15/02/18 08:38, Kieran Bingham wrote: > > From: Kieran Bingham > > > > The D3 supports two LVDS channels. Extend the binding to support them. > > > > Signed-off-by: Kieran Bingham > > --- > > > > Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git > > a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt > > b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt index > > 79860f58a7ad..0dcf488b70df 100644 > > --- a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt > > > > @@ -14,6 +14,7 @@ Required properties: > > - compatible : Shall contain one of > > - "renesas,lvds-r8a7795" for R8A7795 (R-Car H3) compatible LVDS > > encoders > > - "renesas,lvds-r8a7796" for R8A7796 (R-Car M3-W) compatible LVDS > > encoders > > + - "renesas,lvds-r8a77995" for R8A77995 (R-Car D3) compatible LVDS > > encoders > > Hi Laurent, > > Are we unable to have a generic lvds-gen3 here? > > (Although to perhaps answer my own question I see that the D3/E3 have extra > registers) > > Also "lets pretend" that I intentionally separated out the LVDS updates to > the rcar_lvds_of_table :) We could for H3 and M3-W, but as you've noticed D3/E3 differ, and so does V3M. > > - reg: Base address and length for the memory-mapped registers > > - clocks: A phandle + clock-specifier pair for the functional clock -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: laurent.pinchart@ideasonboard.com (Laurent Pinchart) Date: Thu, 15 Feb 2018 16:04:55 +0200 Subject: [PATCH 3/8] dt-bindings: display: renesas, lvds: Add LVDS binding for D3 In-Reply-To: References: <1518683903-10681-1-git-send-email-kbingham@kernel.org> <1518683903-10681-4-git-send-email-kbingham@kernel.org> Message-ID: <3242490.rUUU4MHlpR@avalon> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Kieran, On Thursday, 15 February 2018 10:45:33 EET Kieran Bingham wrote: > On 15/02/18 08:38, Kieran Bingham wrote: > > From: Kieran Bingham > > > > The D3 supports two LVDS channels. Extend the binding to support them. > > > > Signed-off-by: Kieran Bingham > > --- > > > > Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git > > a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt > > b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt index > > 79860f58a7ad..0dcf488b70df 100644 > > --- a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt > > > > @@ -14,6 +14,7 @@ Required properties: > > - compatible : Shall contain one of > > - "renesas,lvds-r8a7795" for R8A7795 (R-Car H3) compatible LVDS > > encoders > > - "renesas,lvds-r8a7796" for R8A7796 (R-Car M3-W) compatible LVDS > > encoders > > + - "renesas,lvds-r8a77995" for R8A77995 (R-Car D3) compatible LVDS > > encoders > > Hi Laurent, > > Are we unable to have a generic lvds-gen3 here? > > (Although to perhaps answer my own question I see that the D3/E3 have extra > registers) > > Also "lets pretend" that I intentionally separated out the LVDS updates to > the rcar_lvds_of_table :) We could for H3 and M3-W, but as you've noticed D3/E3 differ, and so does V3M. > > - reg: Base address and length for the memory-mapped registers > > - clocks: A phandle + clock-specifier pair for the functional clock -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH 3/8] dt-bindings: display: renesas, lvds: Add LVDS binding for D3 Date: Thu, 15 Feb 2018 16:04:55 +0200 Message-ID: <3242490.rUUU4MHlpR@avalon> References: <1518683903-10681-1-git-send-email-kbingham@kernel.org> <1518683903-10681-4-git-send-email-kbingham@kernel.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Kieran Bingham Cc: Mark Rutland , devicetree@vger.kernel.org, Laurent Pinchart , David Airlie , Kieran Bingham , open list , Rob Herring , linux-renesas-soc@vger.kernel.org, Simon Horman , geert@glider.be, "open list:DRM DRIVERS" , Kieran Bingham , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org SGkgS2llcmFuLAoKT24gVGh1cnNkYXksIDE1IEZlYnJ1YXJ5IDIwMTggMTA6NDU6MzMgRUVUIEtp ZXJhbiBCaW5naGFtIHdyb3RlOgo+IE9uIDE1LzAyLzE4IDA4OjM4LCBLaWVyYW4gQmluZ2hhbSB3 cm90ZToKPiA+IEZyb206IEtpZXJhbiBCaW5naGFtIDxraWVyYW4uYmluZ2hhbStyZW5lc2FzQGlk ZWFzb25ib2FyZC5jb20+Cj4gPiAKPiA+IFRoZSBEMyBzdXBwb3J0cyB0d28gTFZEUyBjaGFubmVs cy4gRXh0ZW5kIHRoZSBiaW5kaW5nIHRvIHN1cHBvcnQgdGhlbS4KPiA+IAo+ID4gU2lnbmVkLW9m Zi1ieTogS2llcmFuIEJpbmdoYW0gPGtpZXJhbi5iaW5naGFtK3JlbmVzYXNAaWRlYXNvbmJvYXJk LmNvbT4KPiA+IC0tLQo+ID4gCj4gPiAgRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdz L2Rpc3BsYXkvYnJpZGdlL3JlbmVzYXMsbHZkcy50eHQgfCAxICsKPiA+ICAxIGZpbGUgY2hhbmdl ZCwgMSBpbnNlcnRpb24oKykKPiA+IAo+ID4gZGlmZiAtLWdpdAo+ID4gYS9Eb2N1bWVudGF0aW9u L2RldmljZXRyZWUvYmluZGluZ3MvZGlzcGxheS9icmlkZ2UvcmVuZXNhcyxsdmRzLnR4dAo+ID4g Yi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZGlzcGxheS9icmlkZ2UvcmVuZXNh cyxsdmRzLnR4dCBpbmRleAo+ID4gNzk4NjBmNThhN2FkLi4wZGNmNDg4YjcwZGYgMTAwNjQ0Cj4g PiAtLS0gYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZGlzcGxheS9icmlkZ2Uv cmVuZXNhcyxsdmRzLnR4dAo+ID4gKysrIGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRp bmdzL2Rpc3BsYXkvYnJpZGdlL3JlbmVzYXMsbHZkcy50eHQKPiA+IAo+ID4gQEAgLTE0LDYgKzE0 LDcgQEAgUmVxdWlyZWQgcHJvcGVydGllczoKPiA+ICAtIGNvbXBhdGlibGUgOiBTaGFsbCBjb250 YWluIG9uZSBvZgo+ID4gICAgLSAicmVuZXNhcyxsdmRzLXI4YTc3OTUiIGZvciBSOEE3Nzk1IChS LUNhciBIMykgY29tcGF0aWJsZSBMVkRTCj4gPiAgICBlbmNvZGVycwo+ID4gICAgLSAicmVuZXNh cyxsdmRzLXI4YTc3OTYiIGZvciBSOEE3Nzk2IChSLUNhciBNMy1XKSBjb21wYXRpYmxlIExWRFMK PiA+ICAgIGVuY29kZXJzCj4gPiArICAtICJyZW5lc2FzLGx2ZHMtcjhhNzc5OTUiIGZvciBSOEE3 Nzk5NSAoUi1DYXIgRDMpIGNvbXBhdGlibGUgTFZEUwo+ID4gZW5jb2RlcnMKPiAKPiBIaSBMYXVy ZW50LAo+IAo+IEFyZSB3ZSB1bmFibGUgdG8gaGF2ZSBhIGdlbmVyaWMgbHZkcy1nZW4zIGhlcmU/ Cj4gCj4gKEFsdGhvdWdoIHRvIHBlcmhhcHMgYW5zd2VyIG15IG93biBxdWVzdGlvbiBJIHNlZSB0 aGF0IHRoZSBEMy9FMyBoYXZlIGV4dHJhCj4gcmVnaXN0ZXJzKQo+IAo+IEFsc28gImxldHMgcHJl dGVuZCIgdGhhdCBJIGludGVudGlvbmFsbHkgc2VwYXJhdGVkIG91dCB0aGUgTFZEUyB1cGRhdGVz IHRvCj4gdGhlIHJjYXJfbHZkc19vZl90YWJsZSA6KQoKV2UgY291bGQgZm9yIEgzIGFuZCBNMy1X LCBidXQgYXMgeW91J3ZlIG5vdGljZWQgRDMvRTMgZGlmZmVyLCBhbmQgc28gZG9lcyBWM00uCgo+ ID4gIC0gcmVnOiBCYXNlIGFkZHJlc3MgYW5kIGxlbmd0aCBmb3IgdGhlIG1lbW9yeS1tYXBwZWQg cmVnaXN0ZXJzCj4gPiAgLSBjbG9ja3M6IEEgcGhhbmRsZSArIGNsb2NrLXNwZWNpZmllciBwYWly IGZvciB0aGUgZnVuY3Rpb25hbCBjbG9jawoKLS0gClJlZ2FyZHMsCgpMYXVyZW50IFBpbmNoYXJ0 CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2 ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9s aXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK