From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D4CCC61DA4 for ; Tue, 14 Feb 2023 18:07:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GqTBJbWIqZWieQ0adj80VOdwOcXrZK8irFFVmnhqjhU=; b=0higKsAc48mSeZ momj4Rle/i2B/UhH0PDfZElPn0tOTv/mtw3SmQq9kszRZkLjPedIyzKVSZvPJ2LJW1Xxx8D2CBy6d Bg6rAlSQh5e4+qa3KAolsbKZP1wzFRONa1noEvURw8MEB0Su/g1DZIJM+2vlHX86yneh6ax7IMXRg 14ahjhPnrvU3T9u/xhTzk0zLLRL9/rYqG9h4cIzI/N4hyB6bStTrH5BIHCgDKJCRol5JIdXJzvxIK X2/hBB7oyHaJw6Wgn2wgVlD5g0RgArL5qw7uKFE0qNamsXfOkhmXReoFzS3WeFMtNHwWh0k/wdFxO egKeAyNuEXK//yWH7jvw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pRzhr-0036Le-3a; Tue, 14 Feb 2023 18:07:07 +0000 Received: from madras.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e5ab]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pRzhf-0036IA-Iu; Tue, 14 Feb 2023 18:06:57 +0000 Received: from [192.168.1.90] (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6B8E866020A4; Tue, 14 Feb 2023 18:06:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676398013; bh=ft8PH/ZqA6nSgApIqin+YnV9fYbavSwte6N7D71qPzY=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Tw/5LqZEgofQMm+jUdg1ofHxTTLysSEGiKAK2I5nemTdfdb+gbMdIoqHQBC2up2c7 IQURtYbXkNEgW3EWE5RDCRXlmI7GZ2+JnuRafMUmhIk+Fl9XrDoypvR7x5Q3xnfQKs Tz/AAOZS9L/NcQKckHwdb5WWXm+Q6W3OWUX6SQJ9tT9dWaUr83u0WMhVowSq1cIuJU 2m3NmAatl/MPmyhMUBiG3WbjrJmCeth69VFTvcV17fZHQylzNJDnBjv26rwQ5qGzPP CRTqFqSfedTHbhAElWszPSsMja6HWQypl72R+5CRptn6hKxBjpbQQqimgz6IM5yC7x 9hoBu6favdwZA== Message-ID: <3256853a-d744-4a41-41b6-752b5c95eedc@collabora.com> Date: Tue, 14 Feb 2023 20:06:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [PATCH 05/12] riscv: Implement non-coherent DMA support via SiFive cache flushing Content-Language: en-US To: Ben Dooks , Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> <20230211031821.976408-6-cristian.ciocaltea@collabora.com> From: Cristian Ciocaltea In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230214_100655_902917_C8A65259 X-CRM114-Status: GOOD ( 15.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gMi8xMy8yMyAxMDozMCwgQmVuIERvb2tzIHdyb3RlOgo+IE9uIDExLzAyLzIwMjMgMDM6MTgs IENyaXN0aWFuIENpb2NhbHRlYSB3cm90ZToKPj4gRnJvbTogRW1pbCBSZW5uZXIgQmVydGhpbmcg PGtlcm5lbEBlc21pbC5kaz4KPj4KPj4gVGhpcyB2YXJpYW50IGlzIHVzZWQgb24gdGhlIFN0YXJG aXZlIEpINzEwMCBTb0MuCj4+Cj4+IFNpZ25lZC1vZmYtYnk6IEVtaWwgUmVubmVyIEJlcnRoaW5n IDxrZXJuZWxAZXNtaWwuZGs+Cj4+IFNpZ25lZC1vZmYtYnk6IENyaXN0aWFuIENpb2NhbHRlYSA8 Y3Jpc3RpYW4uY2lvY2FsdGVhQGNvbGxhYm9yYS5jb20+Cj4+IC0tLQo+PiDCoCBhcmNoL3Jpc2N2 L0tjb25maWfCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCB8wqAgNiArKysrLS0KPj4gwqAgYXJj aC9yaXNjdi9tbS9kbWEtbm9uY29oZXJlbnQuYyB8IDM3ICsrKysrKysrKysrKysrKysrKysrKysr KysrKysrKystLQo+PiDCoCAyIGZpbGVzIGNoYW5nZWQsIDM5IGluc2VydGlvbnMoKyksIDQgZGVs ZXRpb25zKC0pCj4+Cj4+IGRpZmYgLS1naXQgYS9hcmNoL3Jpc2N2L0tjb25maWcgYi9hcmNoL3Jp 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(Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6B8E866020A4; Tue, 14 Feb 2023 18:06:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676398013; bh=ft8PH/ZqA6nSgApIqin+YnV9fYbavSwte6N7D71qPzY=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Tw/5LqZEgofQMm+jUdg1ofHxTTLysSEGiKAK2I5nemTdfdb+gbMdIoqHQBC2up2c7 IQURtYbXkNEgW3EWE5RDCRXlmI7GZ2+JnuRafMUmhIk+Fl9XrDoypvR7x5Q3xnfQKs Tz/AAOZS9L/NcQKckHwdb5WWXm+Q6W3OWUX6SQJ9tT9dWaUr83u0WMhVowSq1cIuJU 2m3NmAatl/MPmyhMUBiG3WbjrJmCeth69VFTvcV17fZHQylzNJDnBjv26rwQ5qGzPP CRTqFqSfedTHbhAElWszPSsMja6HWQypl72R+5CRptn6hKxBjpbQQqimgz6IM5yC7x 9hoBu6favdwZA== Message-ID: <3256853a-d744-4a41-41b6-752b5c95eedc@collabora.com> Date: Tue, 14 Feb 2023 20:06:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [PATCH 05/12] riscv: Implement non-coherent DMA support via SiFive cache flushing Content-Language: en-US To: Ben Dooks , Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> <20230211031821.976408-6-cristian.ciocaltea@collabora.com> From: Cristian Ciocaltea In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230214_100655_902917_C8A65259 X-CRM114-Status: GOOD ( 15.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gMi8xMy8yMyAxMDozMCwgQmVuIERvb2tzIHdyb3RlOgo+IE9uIDExLzAyLzIwMjMgMDM6MTgs IENyaXN0aWFuIENpb2NhbHRlYSB3cm90ZToKPj4gRnJvbTogRW1pbCBSZW5uZXIgQmVydGhpbmcg PGtlcm5lbEBlc21pbC5kaz4KPj4KPj4gVGhpcyB2YXJpYW50IGlzIHVzZWQgb24gdGhlIFN0YXJG aXZlIEpINzEwMCBTb0MuCj4+Cj4+IFNpZ25lZC1vZmYtYnk6IEVtaWwgUmVubmVyIEJlcnRoaW5n IDxrZXJuZWxAZXNtaWwuZGs+Cj4+IFNpZ25lZC1vZmYtYnk6IENyaXN0aWFuIENpb2NhbHRlYSA8 Y3Jpc3RpYW4uY2lvY2FsdGVhQGNvbGxhYm9yYS5jb20+Cj4+IC0tLQo+PiDCoCBhcmNoL3Jpc2N2 L0tjb25maWfCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCB8wqAgNiArKysrLS0KPj4gwqAgYXJj aC9yaXNjdi9tbS9kbWEtbm9uY29oZXJlbnQuYyB8IDM3ICsrKysrKysrKysrKysrKysrKysrKysr KysrKysrKystLQo+PiDCoCAyIGZpbGVzIGNoYW5nZWQsIDM5IGluc2VydGlvbnMoKyksIDQgZGVs ZXRpb25zKC0pCj4+Cj4+IGRpZmYgLS1naXQgYS9hcmNoL3Jpc2N2L0tjb25maWcgYi9hcmNoL3Jp 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[192.168.1.90] (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6B8E866020A4; Tue, 14 Feb 2023 18:06:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676398013; bh=ft8PH/ZqA6nSgApIqin+YnV9fYbavSwte6N7D71qPzY=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Tw/5LqZEgofQMm+jUdg1ofHxTTLysSEGiKAK2I5nemTdfdb+gbMdIoqHQBC2up2c7 IQURtYbXkNEgW3EWE5RDCRXlmI7GZ2+JnuRafMUmhIk+Fl9XrDoypvR7x5Q3xnfQKs Tz/AAOZS9L/NcQKckHwdb5WWXm+Q6W3OWUX6SQJ9tT9dWaUr83u0WMhVowSq1cIuJU 2m3NmAatl/MPmyhMUBiG3WbjrJmCeth69VFTvcV17fZHQylzNJDnBjv26rwQ5qGzPP CRTqFqSfedTHbhAElWszPSsMja6HWQypl72R+5CRptn6hKxBjpbQQqimgz6IM5yC7x 9hoBu6favdwZA== Message-ID: <3256853a-d744-4a41-41b6-752b5c95eedc@collabora.com> Date: Tue, 14 Feb 2023 20:06:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [PATCH 05/12] riscv: Implement non-coherent DMA support via SiFive cache flushing Content-Language: en-US To: Ben Dooks , Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> <20230211031821.976408-6-cristian.ciocaltea@collabora.com> From: Cristian Ciocaltea In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2/13/23 10:30, Ben Dooks wrote: > On 11/02/2023 03:18, Cristian Ciocaltea wrote: >> From: Emil Renner Berthing >> >> This variant is used on the StarFive JH7100 SoC. >> >> Signed-off-by: Emil Renner Berthing >> Signed-off-by: Cristian Ciocaltea >> --- >>   arch/riscv/Kconfig              |  6 ++++-- >>   arch/riscv/mm/dma-noncoherent.c | 37 +++++++++++++++++++++++++++++++-- >>   2 files changed, 39 insertions(+), 4 deletions(-) >> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >> index 9c687da7756d..05f6c77faf6f 100644 >> --- a/arch/riscv/Kconfig >> +++ b/arch/riscv/Kconfig >> @@ -232,12 +232,14 @@ config LOCKDEP_SUPPORT >>       def_bool y >>   config RISCV_DMA_NONCOHERENT >> -    bool >> +    bool "Support non-coherent DMA" >> +    default SOC_STARFIVE >>       select ARCH_HAS_DMA_PREP_COHERENT >> +    select ARCH_HAS_DMA_SET_UNCACHED >> +    select ARCH_HAS_DMA_CLEAR_UNCACHED >>       select ARCH_HAS_SYNC_DMA_FOR_DEVICE >>       select ARCH_HAS_SYNC_DMA_FOR_CPU >>       select ARCH_HAS_SETUP_DMA_OPS >> -    select DMA_DIRECT_REMAP >>   config AS_HAS_INSN >>       def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) >> t0$(comma) t0$(comma) zero) >> diff --git a/arch/riscv/mm/dma-noncoherent.c >> b/arch/riscv/mm/dma-noncoherent.c >> index d919efab6eba..e07e53aea537 100644 >> --- a/arch/riscv/mm/dma-noncoherent.c >> +++ b/arch/riscv/mm/dma-noncoherent.c >> @@ -9,14 +9,21 @@ >>   #include >>   #include >>   #include >> +#include >>   static bool noncoherent_supported; >>   void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, >>                     enum dma_data_direction dir) >>   { >> -    void *vaddr = phys_to_virt(paddr); >> +    void *vaddr; >> +    if (sifive_ccache_handle_noncoherent()) { >> +        sifive_ccache_flush_range(paddr, size); >> +        return; >> +    } >> + >> +    vaddr = phys_to_virt(paddr); >>       switch (dir) { >>       case DMA_TO_DEVICE: >>           ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); >> @@ -35,8 +42,14 @@ void arch_sync_dma_for_device(phys_addr_t paddr, >> size_t size, >>   void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, >>                  enum dma_data_direction dir) >>   { >> -    void *vaddr = phys_to_virt(paddr); >> +    void *vaddr; >> + >> +    if (sifive_ccache_handle_noncoherent()) { >> +        sifive_ccache_flush_range(paddr, size); >> +        return; >> +    } > > ok, what happens if we have an system where the ccache and another level > of cache also requires maintenance operations? According to [1], the handling of non-coherent DMA on RISC-V is currently being worked on, so I will respin the series as soon as the proper support arrives. [1] https://lore.kernel.org/lkml/Y+d36nz0xdfXmDI1@spud/ >> +    vaddr = phys_to_virt(paddr); >>       switch (dir) { >>       case DMA_TO_DEVICE: >>           break; >> @@ -49,10 +62,30 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, >> size_t size, >>       } >>   } >> +void *arch_dma_set_uncached(void *addr, size_t size) >> +{ >> +    if (sifive_ccache_handle_noncoherent()) >> +        return sifive_ccache_set_uncached(addr, size); >> + >> +    return addr; >> +} >> + >> +void arch_dma_clear_uncached(void *addr, size_t size) >> +{ >> +    if (sifive_ccache_handle_noncoherent()) >> +        sifive_ccache_clear_uncached(addr, size); >> +} >> + >>   void arch_dma_prep_coherent(struct page *page, size_t size) >>   { >>       void *flush_addr = page_address(page); >> +    if (sifive_ccache_handle_noncoherent()) { >> +        memset(flush_addr, 0, size); >> +        sifive_ccache_flush_range(__pa(flush_addr), size); >> +        return; >> +    } >> + >>       ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); >>   } >