diff for duplicates of <3286748.Col0jAfKKX@phil> diff --git a/a/1.txt b/N1/1.txt index 757480d..95087a1 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,65 +1,58 @@ -Am Dienstag, 1. M=E4rz 2016, 18:14:33 schrieb Xing Zheng: +Am Dienstag, 1. März 2016, 18:14:33 schrieb Xing Zheng: > The rk3399's pll and clock are similar with rk3036's, it different > with base on the rk3066(rk3188, rk3288, rk3368 use it), there are > different adjust foctors and control registers, so these should be > independent and separate from the series of rk3066s. ->=20 +> > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> [...] -> +static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *p= -ll, -> +=09=09=09=09const struct rockchip_pll_rate_table *rate) +> +static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, +> + const struct rockchip_pll_rate_table *rate) > +{ -> +=09const struct clk_ops *pll_mux_ops =3D pll->pll_mux_ops; -> +=09struct clk_mux *pll_mux =3D &pll->pll_mux; -> +=09struct rockchip_pll_rate_table cur; -> +=09u32 pllcon; -> +=09int rate_change_remuxed =3D 0; -> +=09int cur_parent; -> +=09int ret; +> + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; +> + struct clk_mux *pll_mux = &pll->pll_mux; +> + struct rockchip_pll_rate_table cur; +> + u32 pllcon; +> + int rate_change_remuxed = 0; +> + int cur_parent; +> + int ret; > + -> +=09pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refd= -iv: %d, -> postdiv2: %d, dsmpd: %d, frac: %d\n", +=09=09__func__, rate->rate, -> rate->fbdiv, rate->postdiv1, rate->refdiv, +=09=09rate->postdiv2, +> + pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, +> postdiv2: %d, dsmpd: %d, frac: %d\n", + __func__, rate->rate, +> rate->fbdiv, rate->postdiv1, rate->refdiv, + rate->postdiv2, > rate->dsmpd, rate->frac); > + -> +=09rockchip_rk3399_pll_get_params(pll, &cur); -> +=09cur.rate =3D 0; +> + rockchip_rk3399_pll_get_params(pll, &cur); +> + cur.rate = 0; > + -> +=09cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw); -> +=09if (cur_parent =3D=3D PLL_MODE_NORM) { -> +=09=09pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); -> +=09=09rate_change_remuxed =3D 1; -> +=09} +> + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); +> + if (cur_parent == PLL_MODE_NORM) { +> + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); +> + rate_change_remuxed = 1; +> + } > + -> +=09/* update pll values */ -> +=09writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MA= -SK, -> +=09=09=09=09=09 RK3399_PLLCON0_FBDIV_SHIFT), +> + /* update pll values */ +> + writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, +> + RK3399_PLLCON0_FBDIV_SHIFT), -indentation is strange ... I guess the plan was to move=20 -RK3399_PLLCON0_FBDIV_SHIFT under RK3399_PLLCON0_FBDIV_MASK, currently i= -t's=20 +indentation is strange ... I guess the plan was to move +RK3399_PLLCON0_FBDIV_SHIFT under RK3399_PLLCON0_FBDIV_MASK, currently it's having tabs + spaces but has no alignment whatsoever -> +=09=09 pll->reg_base + RK3399_PLLCON(0)); +> + pll->reg_base + RK3399_PLLCON(0)); > + -> +=09writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_= -MASK, -> +=09=09=09=09=09=09 RK3399_PLLCON1_REFDIV_SHIFT) | -> +=09=09 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_M= -ASK, -> +=09=09=09=09=09 RK3399_PLLCON1_POSTDIV1_SHIFT) | +> + writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, +> + RK3399_PLLCON1_REFDIV_SHIFT) | +> + HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, +> + RK3399_PLLCON1_POSTDIV1_SHIFT) | same for postdiv1 -> +=09=09 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_M= -ASK, -> +=09=09=09=09=09=09 RK3399_PLLCON1_POSTDIV2_SHIFT), -> +=09=09 pll->reg_base + RK3399_PLLCON(1)); +> + HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, +> + RK3399_PLLCON1_POSTDIV2_SHIFT), +> + pll->reg_base + RK3399_PLLCON(1)); rest looks nice diff --git a/a/content_digest b/N1/content_digest index 9e8b7a0..dac1779 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -15,68 +15,61 @@ " linux-kernel@vger.kernel.org\0" "\00:1\0" "b\0" - "Am Dienstag, 1. M=E4rz 2016, 18:14:33 schrieb Xing Zheng:\n" + "Am Dienstag, 1. M\303\244rz 2016, 18:14:33 schrieb Xing Zheng:\n" "> The rk3399's pll and clock are similar with rk3036's, it different\n" "> with base on the rk3066(rk3188, rk3288, rk3368 use it), there are\n" "> different adjust foctors and control registers, so these should be\n" "> independent and separate from the series of rk3066s.\n" - ">=20\n" + "> \n" "> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>\n" "\n" "[...]\n" "\n" - "> +static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *p=\n" - "ll,\n" - "> +=09=09=09=09const struct rockchip_pll_rate_table *rate)\n" + "> +static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,\n" + "> +\t\t\t\tconst struct rockchip_pll_rate_table *rate)\n" "> +{\n" - "> +=09const struct clk_ops *pll_mux_ops =3D pll->pll_mux_ops;\n" - "> +=09struct clk_mux *pll_mux =3D &pll->pll_mux;\n" - "> +=09struct rockchip_pll_rate_table cur;\n" - "> +=09u32 pllcon;\n" - "> +=09int rate_change_remuxed =3D 0;\n" - "> +=09int cur_parent;\n" - "> +=09int ret;\n" + "> +\tconst struct clk_ops *pll_mux_ops = pll->pll_mux_ops;\n" + "> +\tstruct clk_mux *pll_mux = &pll->pll_mux;\n" + "> +\tstruct rockchip_pll_rate_table cur;\n" + "> +\tu32 pllcon;\n" + "> +\tint rate_change_remuxed = 0;\n" + "> +\tint cur_parent;\n" + "> +\tint ret;\n" "> +\n" - "> +=09pr_debug(\"%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refd=\n" - "iv: %d,\n" - "> postdiv2: %d, dsmpd: %d, frac: %d\\n\", +=09=09__func__, rate->rate,\n" - "> rate->fbdiv, rate->postdiv1, rate->refdiv, +=09=09rate->postdiv2,\n" + "> +\tpr_debug(\"%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d,\n" + "> postdiv2: %d, dsmpd: %d, frac: %d\\n\", +\t\t__func__, rate->rate,\n" + "> rate->fbdiv, rate->postdiv1, rate->refdiv, +\t\trate->postdiv2,\n" "> rate->dsmpd, rate->frac);\n" "> +\n" - "> +=09rockchip_rk3399_pll_get_params(pll, &cur);\n" - "> +=09cur.rate =3D 0;\n" + "> +\trockchip_rk3399_pll_get_params(pll, &cur);\n" + "> +\tcur.rate = 0;\n" "> +\n" - "> +=09cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw);\n" - "> +=09if (cur_parent =3D=3D PLL_MODE_NORM) {\n" - "> +=09=09pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);\n" - "> +=09=09rate_change_remuxed =3D 1;\n" - "> +=09}\n" + "> +\tcur_parent = pll_mux_ops->get_parent(&pll_mux->hw);\n" + "> +\tif (cur_parent == PLL_MODE_NORM) {\n" + "> +\t\tpll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);\n" + "> +\t\trate_change_remuxed = 1;\n" + "> +\t}\n" "> +\n" - "> +=09/* update pll values */\n" - "> +=09writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MA=\n" - "SK,\n" - "> +=09=09=09=09=09 RK3399_PLLCON0_FBDIV_SHIFT),\n" + "> +\t/* update pll values */\n" + "> +\twritel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,\n" + "> +\t\t\t\t\t RK3399_PLLCON0_FBDIV_SHIFT),\n" "\n" - "indentation is strange ... I guess the plan was to move=20\n" - "RK3399_PLLCON0_FBDIV_SHIFT under RK3399_PLLCON0_FBDIV_MASK, currently i=\n" - "t's=20\n" + "indentation is strange ... I guess the plan was to move \n" + "RK3399_PLLCON0_FBDIV_SHIFT under RK3399_PLLCON0_FBDIV_MASK, currently it's \n" "having tabs + spaces but has no alignment whatsoever\n" "\n" - "> +=09=09 pll->reg_base + RK3399_PLLCON(0));\n" + "> +\t\t pll->reg_base + RK3399_PLLCON(0));\n" "> +\n" - "> +=09writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_=\n" - "MASK,\n" - "> +=09=09=09=09=09=09 RK3399_PLLCON1_REFDIV_SHIFT) |\n" - "> +=09=09 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_M=\n" - "ASK,\n" - "> +=09=09=09=09=09 RK3399_PLLCON1_POSTDIV1_SHIFT) |\n" + "> +\twritel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,\n" + "> +\t\t\t\t\t\t RK3399_PLLCON1_REFDIV_SHIFT) |\n" + "> +\t\t HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,\n" + "> +\t\t\t\t\t RK3399_PLLCON1_POSTDIV1_SHIFT) |\n" "\n" "same for postdiv1\n" "\n" - "> +=09=09 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_M=\n" - "ASK,\n" - "> +=09=09=09=09=09=09 RK3399_PLLCON1_POSTDIV2_SHIFT),\n" - "> +=09=09 pll->reg_base + RK3399_PLLCON(1));\n" + "> +\t\t HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,\n" + "> +\t\t\t\t\t\t RK3399_PLLCON1_POSTDIV2_SHIFT),\n" + "> +\t\t pll->reg_base + RK3399_PLLCON(1));\n" "\n" "\n" "rest looks nice\n" @@ -84,4 +77,4 @@ "\n" Heiko -c0100f71bbb280f715bdcc5cc42083ba9f0bf3bdb63e5f687d95c767b3ba3a83 +552461fb5cfd9b8b253cfeaa039451003bdba5a5f1146ba890aba89c2416316b
diff --git a/a/1.txt b/N2/1.txt index 757480d..4907f4d 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,65 +1,58 @@ -Am Dienstag, 1. M=E4rz 2016, 18:14:33 schrieb Xing Zheng: +Am Dienstag, 1. M?rz 2016, 18:14:33 schrieb Xing Zheng: > The rk3399's pll and clock are similar with rk3036's, it different > with base on the rk3066(rk3188, rk3288, rk3368 use it), there are > different adjust foctors and control registers, so these should be > independent and separate from the series of rk3066s. ->=20 +> > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> [...] -> +static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *p= -ll, -> +=09=09=09=09const struct rockchip_pll_rate_table *rate) +> +static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, +> + const struct rockchip_pll_rate_table *rate) > +{ -> +=09const struct clk_ops *pll_mux_ops =3D pll->pll_mux_ops; -> +=09struct clk_mux *pll_mux =3D &pll->pll_mux; -> +=09struct rockchip_pll_rate_table cur; -> +=09u32 pllcon; -> +=09int rate_change_remuxed =3D 0; -> +=09int cur_parent; -> +=09int ret; +> + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; +> + struct clk_mux *pll_mux = &pll->pll_mux; +> + struct rockchip_pll_rate_table cur; +> + u32 pllcon; +> + int rate_change_remuxed = 0; +> + int cur_parent; +> + int ret; > + -> +=09pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refd= -iv: %d, -> postdiv2: %d, dsmpd: %d, frac: %d\n", +=09=09__func__, rate->rate, -> rate->fbdiv, rate->postdiv1, rate->refdiv, +=09=09rate->postdiv2, +> + pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, +> postdiv2: %d, dsmpd: %d, frac: %d\n", + __func__, rate->rate, +> rate->fbdiv, rate->postdiv1, rate->refdiv, + rate->postdiv2, > rate->dsmpd, rate->frac); > + -> +=09rockchip_rk3399_pll_get_params(pll, &cur); -> +=09cur.rate =3D 0; +> + rockchip_rk3399_pll_get_params(pll, &cur); +> + cur.rate = 0; > + -> +=09cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw); -> +=09if (cur_parent =3D=3D PLL_MODE_NORM) { -> +=09=09pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); -> +=09=09rate_change_remuxed =3D 1; -> +=09} +> + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); +> + if (cur_parent == PLL_MODE_NORM) { +> + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); +> + rate_change_remuxed = 1; +> + } > + -> +=09/* update pll values */ -> +=09writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MA= -SK, -> +=09=09=09=09=09 RK3399_PLLCON0_FBDIV_SHIFT), +> + /* update pll values */ +> + writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, +> + RK3399_PLLCON0_FBDIV_SHIFT), -indentation is strange ... I guess the plan was to move=20 -RK3399_PLLCON0_FBDIV_SHIFT under RK3399_PLLCON0_FBDIV_MASK, currently i= -t's=20 +indentation is strange ... I guess the plan was to move +RK3399_PLLCON0_FBDIV_SHIFT under RK3399_PLLCON0_FBDIV_MASK, currently it's having tabs + spaces but has no alignment whatsoever -> +=09=09 pll->reg_base + RK3399_PLLCON(0)); +> + pll->reg_base + RK3399_PLLCON(0)); > + -> +=09writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_= -MASK, -> +=09=09=09=09=09=09 RK3399_PLLCON1_REFDIV_SHIFT) | -> +=09=09 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_M= -ASK, -> +=09=09=09=09=09 RK3399_PLLCON1_POSTDIV1_SHIFT) | +> + writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, +> + RK3399_PLLCON1_REFDIV_SHIFT) | +> + HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, +> + RK3399_PLLCON1_POSTDIV1_SHIFT) | same for postdiv1 -> +=09=09 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_M= -ASK, -> +=09=09=09=09=09=09 RK3399_PLLCON1_POSTDIV2_SHIFT), -> +=09=09 pll->reg_base + RK3399_PLLCON(1)); +> + HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, +> + RK3399_PLLCON1_POSTDIV2_SHIFT), +> + pll->reg_base + RK3399_PLLCON(1)); rest looks nice diff --git a/a/content_digest b/N2/content_digest index 9e8b7a0..9525682 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,82 +1,66 @@ "ref\01456827275-8035-1-git-send-email-zhengxing@rock-chips.com\0" "ref\01456827275-8035-4-git-send-email-zhengxing@rock-chips.com\0" - "From\0Heiko Stuebner <heiko@sntech.de>\0" - "Subject\0Re: [RESEND PATCH v2 3/5] clk: rockchip: add new pll-type for rk3399 and similar socs\0" + "From\0heiko@sntech.de (Heiko Stuebner)\0" + "Subject\0[RESEND PATCH v2 3/5] clk: rockchip: add new pll-type for rk3399 and similar socs\0" "Date\0Wed, 09 Mar 2016 02:22:50 +0100\0" - "To\0Xing Zheng <zhengxing@rock-chips.com>\0" - "Cc\0linux-rockchip@lists.infradead.org" - huangtao@rock-chips.com - jay.xu@rock-chips.com - elaine.zhang@rock-chips.com - Michael Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "Am Dienstag, 1. M=E4rz 2016, 18:14:33 schrieb Xing Zheng:\n" + "Am Dienstag, 1. M?rz 2016, 18:14:33 schrieb Xing Zheng:\n" "> The rk3399's pll and clock are similar with rk3036's, it different\n" "> with base on the rk3066(rk3188, rk3288, rk3368 use it), there are\n" "> different adjust foctors and control registers, so these should be\n" "> independent and separate from the series of rk3066s.\n" - ">=20\n" + "> \n" "> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>\n" "\n" "[...]\n" "\n" - "> +static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *p=\n" - "ll,\n" - "> +=09=09=09=09const struct rockchip_pll_rate_table *rate)\n" + "> +static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,\n" + "> +\t\t\t\tconst struct rockchip_pll_rate_table *rate)\n" "> +{\n" - "> +=09const struct clk_ops *pll_mux_ops =3D pll->pll_mux_ops;\n" - "> +=09struct clk_mux *pll_mux =3D &pll->pll_mux;\n" - "> +=09struct rockchip_pll_rate_table cur;\n" - "> +=09u32 pllcon;\n" - "> +=09int rate_change_remuxed =3D 0;\n" - "> +=09int cur_parent;\n" - "> +=09int ret;\n" + "> +\tconst struct clk_ops *pll_mux_ops = pll->pll_mux_ops;\n" + "> +\tstruct clk_mux *pll_mux = &pll->pll_mux;\n" + "> +\tstruct rockchip_pll_rate_table cur;\n" + "> +\tu32 pllcon;\n" + "> +\tint rate_change_remuxed = 0;\n" + "> +\tint cur_parent;\n" + "> +\tint ret;\n" "> +\n" - "> +=09pr_debug(\"%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refd=\n" - "iv: %d,\n" - "> postdiv2: %d, dsmpd: %d, frac: %d\\n\", +=09=09__func__, rate->rate,\n" - "> rate->fbdiv, rate->postdiv1, rate->refdiv, +=09=09rate->postdiv2,\n" + "> +\tpr_debug(\"%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d,\n" + "> postdiv2: %d, dsmpd: %d, frac: %d\\n\", +\t\t__func__, rate->rate,\n" + "> rate->fbdiv, rate->postdiv1, rate->refdiv, +\t\trate->postdiv2,\n" "> rate->dsmpd, rate->frac);\n" "> +\n" - "> +=09rockchip_rk3399_pll_get_params(pll, &cur);\n" - "> +=09cur.rate =3D 0;\n" + "> +\trockchip_rk3399_pll_get_params(pll, &cur);\n" + "> +\tcur.rate = 0;\n" "> +\n" - "> +=09cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw);\n" - "> +=09if (cur_parent =3D=3D PLL_MODE_NORM) {\n" - "> +=09=09pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);\n" - "> +=09=09rate_change_remuxed =3D 1;\n" - "> +=09}\n" + "> +\tcur_parent = pll_mux_ops->get_parent(&pll_mux->hw);\n" + "> +\tif (cur_parent == PLL_MODE_NORM) {\n" + "> +\t\tpll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);\n" + "> +\t\trate_change_remuxed = 1;\n" + "> +\t}\n" "> +\n" - "> +=09/* update pll values */\n" - "> +=09writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MA=\n" - "SK,\n" - "> +=09=09=09=09=09 RK3399_PLLCON0_FBDIV_SHIFT),\n" + "> +\t/* update pll values */\n" + "> +\twritel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,\n" + "> +\t\t\t\t\t RK3399_PLLCON0_FBDIV_SHIFT),\n" "\n" - "indentation is strange ... I guess the plan was to move=20\n" - "RK3399_PLLCON0_FBDIV_SHIFT under RK3399_PLLCON0_FBDIV_MASK, currently i=\n" - "t's=20\n" + "indentation is strange ... I guess the plan was to move \n" + "RK3399_PLLCON0_FBDIV_SHIFT under RK3399_PLLCON0_FBDIV_MASK, currently it's \n" "having tabs + spaces but has no alignment whatsoever\n" "\n" - "> +=09=09 pll->reg_base + RK3399_PLLCON(0));\n" + "> +\t\t pll->reg_base + RK3399_PLLCON(0));\n" "> +\n" - "> +=09writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_=\n" - "MASK,\n" - "> +=09=09=09=09=09=09 RK3399_PLLCON1_REFDIV_SHIFT) |\n" - "> +=09=09 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_M=\n" - "ASK,\n" - "> +=09=09=09=09=09 RK3399_PLLCON1_POSTDIV1_SHIFT) |\n" + "> +\twritel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,\n" + "> +\t\t\t\t\t\t RK3399_PLLCON1_REFDIV_SHIFT) |\n" + "> +\t\t HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,\n" + "> +\t\t\t\t\t RK3399_PLLCON1_POSTDIV1_SHIFT) |\n" "\n" "same for postdiv1\n" "\n" - "> +=09=09 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_M=\n" - "ASK,\n" - "> +=09=09=09=09=09=09 RK3399_PLLCON1_POSTDIV2_SHIFT),\n" - "> +=09=09 pll->reg_base + RK3399_PLLCON(1));\n" + "> +\t\t HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,\n" + "> +\t\t\t\t\t\t RK3399_PLLCON1_POSTDIV2_SHIFT),\n" + "> +\t\t pll->reg_base + RK3399_PLLCON(1));\n" "\n" "\n" "rest looks nice\n" @@ -84,4 +68,4 @@ "\n" Heiko -c0100f71bbb280f715bdcc5cc42083ba9f0bf3bdb63e5f687d95c767b3ba3a83 +1f4ba721b61fe5db4a213f87ca6911637b687de3e802c034f8e83a1d32b31eb4
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.