From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Schwierzeck Date: Sun, 28 Oct 2018 20:02:28 +0100 Subject: [U-Boot] [PATCH 03/14] mips: mt76xx: Enable SYS_MIPS_CACHE_INIT_RAM_LOAD for cache init In-Reply-To: <20181009065916.31977-3-sr@denx.de> References: <20181009065916.31977-1-sr@denx.de> <20181009065916.31977-3-sr@denx.de> Message-ID: <32b2bb17-cfe5-8319-c240-d65108183abc@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Am 09.10.18 um 08:59 schrieb Stefan Roese: > Using CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD should ensure that the cache > is initialized correctly (parity etc). Even though some issues are > still seen on the linkit and gardena MT7688 platforms, which could > be a result of a non-optimal cache configuration / setup. I thought this doesn't really help? Also if you can't move CONFIG_MIPS_CACHE_INDEX_BASE to some SRAM space, you need to run your memory init code before the cache initialisation to have working DRAM available. But this slows down the boot time. > > Signed-off-by: Stefan Roese > Cc: Daniel Schwierzeck > --- > arch/mips/mach-mt7620/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig > index 13a7bd2cc0..e42d918ba0 100644 > --- a/arch/mips/mach-mt7620/Kconfig > +++ b/arch/mips/mach-mt7620/Kconfig > @@ -13,6 +13,7 @@ choice > config SOC_MT7620 > bool "MT7620/8" > select MIPS_L1_CACHE_SHIFT_5 > + select SYS_MIPS_CACHE_INIT_RAM_LOAD > help > This supports MediaTek MIPS MT7620 family. > > -- - Daniel -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: OpenPGP digital signature URL: