From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Stuebner Subject: Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs Date: Fri, 14 Jun 2019 11:52:25 +0200 Message-ID: <3309819.J5kelTtX6q@phil> References: <20190529074752.19388-1-jay.xu@rock-chips.com> <20190530000848.28106-1-jay.xu@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: In-Reply-To: <20190530000848.28106-1-jay.xu@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org To: Jianqun Xu Cc: mark.rutland@arm.com, robh+dt@kernel.org, zhangzj@rock-chips.com, manivannan.sadhasivam@linaro.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org List-Id: linux-rockchip.vger.kernel.org Hi Jianqun, Am Donnerstag, 30. Mai 2019, 02:08:48 CEST schrieb Jianqun Xu: > This patch adds core dtsi file for Rockchip RK3399Pro SoCs, > include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to > talk to NPU part inside SoC. > > Signed-off-by: Jianqun Xu could you add the necessary pinctrl entry, as suggested by Manivannan? Thanks Heiko > --- > changes since v2: > - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan > > changes since v1: > - remove dfi and dmc > > arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > new file mode 100644 > index 000000000000..bb5ebf6608b9 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. > + > +#include "rk3399.dtsi" > + > +/ { > + compatible = "rockchip,rk3399pro"; > +}; > + > +/* Default to enabled since AP talk to NPU part over pcie */ > +&pcie_phy { > + status = "okay"; > +}; > + > +/* Default to enabled since AP talk to NPU part over pcie */ > +&pcie0 { > + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; > + num-lanes = <4>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie_clkreqn_cpm>; > + status = "okay"; > +}; > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28B56C31E44 for ; Fri, 14 Jun 2019 09:52:36 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 01AB8208CA for ; Fri, 14 Jun 2019 09:52:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="bcY0TGza" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 01AB8208CA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sntech.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WXkw6QEY4DQdj50yLzqqc3cjBLC3YHYhYea+LzLX4F0=; b=bcY0TGza8S9Nck 5QgmXNn8ncdOThy4R3//MDF0VLxbE6p4ZBzoTMTKgt63eq8R7wMborOHpC5Qk8Bc+2o2ILydx5om1 eWNKPvPjbFceIbclIxPdapEVIfTQtxobfd9YP2I44gUMc3kYA3CHHSgsY6RoT+Zy5IJxeJIclKonp oq6TvWZmhWZQwWM5DpYxGyZIHJOw45IUS4zqmu2UsUSRU8DG0AyHBd3UBRKB3+CZBV95MqOaOjo3J ehKoCLiSwCFf2rcxB9hnhELFOp2z3cw6jGXN58W2shU2vhXUfquv349DefgjkumbpcnpJ3XjCMBfD uIzgJ/hfQQUfERkBzC9w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hbist-0000Ma-7p; Fri, 14 Jun 2019 09:52:35 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hbiso-0000LG-0I; Fri, 14 Jun 2019 09:52:31 +0000 Received: from we0305.dip.tu-dresden.de ([141.76.177.49] helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1hbisk-0004H9-GQ; Fri, 14 Jun 2019 11:52:26 +0200 From: Heiko Stuebner To: Jianqun Xu Subject: Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs Date: Fri, 14 Jun 2019 11:52:25 +0200 Message-ID: <3309819.J5kelTtX6q@phil> In-Reply-To: <20190530000848.28106-1-jay.xu@rock-chips.com> References: <20190529074752.19388-1-jay.xu@rock-chips.com> <20190530000848.28106-1-jay.xu@rock-chips.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190614_025230_196789_04890A08 X-CRM114-Status: GOOD ( 14.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, zhangzj@rock-chips.com, linux-rockchip@lists.infradead.org, robh+dt@kernel.org, manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Jianqun, Am Donnerstag, 30. Mai 2019, 02:08:48 CEST schrieb Jianqun Xu: > This patch adds core dtsi file for Rockchip RK3399Pro SoCs, > include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to > talk to NPU part inside SoC. > > Signed-off-by: Jianqun Xu could you add the necessary pinctrl entry, as suggested by Manivannan? Thanks Heiko > --- > changes since v2: > - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan > > changes since v1: > - remove dfi and dmc > > arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > new file mode 100644 > index 000000000000..bb5ebf6608b9 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. > + > +#include "rk3399.dtsi" > + > +/ { > + compatible = "rockchip,rk3399pro"; > +}; > + > +/* Default to enabled since AP talk to NPU part over pcie */ > +&pcie_phy { > + status = "okay"; > +}; > + > +/* Default to enabled since AP talk to NPU part over pcie */ > +&pcie0 { > + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; > + num-lanes = <4>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie_clkreqn_cpm>; > + status = "okay"; > +}; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel