From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87CA5C53219 for ; Wed, 29 Jul 2026 15:20:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pEHtbymeQ8QLdpZRjJMxCPFZkAtSLgPiOJad1Ea2n8M=; b=L0dNjC30qKNq6A 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b=S/3Q0Bnq4xPJ4O8no5JeqAx3On L9u7qtyvrLbPLK4sNmOsNDmzx9YGxap/s+dXIkE2DVu1ePPrSMnIV79P7QE9N5XcLzNxY09nJ3xCF rEEgJamiwBjfHBhSX9+f8Bz+22fl2aj3ZRymXrTXZIV2N+Thzq55RYVYtQhl50/RwmGEKqAe5Bhi9 qZ+EKCMhKWJ0nD4k4/RSkthYkuh2tL43W+0nlOMTkyxN9NjgW8j2PDHfREpLbzMmdW36IwtGhWVVG i/W+ZxBUrMtVlZieZ0H0WZJ/58Ih5M3OwisS3zcDQ/thjEONoREPev7ACzSt4YaVIO6oJmSsSWMJj FRPC5c7g==; From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: tomeu@tomeuvizoso.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, Jiaxing Hu Cc: chaoyi.chen@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: Re: [RFC PATCH v2 2/8] pmdomain/rockchip: add optional per-domain power-on settle delay Date: Wed, 29 Jul 2026 17:20:20 +0200 Message-ID: <3322194.D8ZAKjAxdT@diego> In-Reply-To: <20260718031146.3368811-3-gahing@gahingwoo.com> References: <20260718031146.3368811-1-gahing@gahingwoo.com> <20260718031146.3368811-3-gahing@gahingwoo.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260729_082040_399159_1139C448 X-CRM114-Status: GOOD ( 23.32 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org QW0gU2Ftc3RhZywgMTguIEp1bGkgMjAyNiwgMDU6MTE6NDAgTWl0dGVsZXVyb3DDpGlzY2hlIFNv bW1lcnplaXQgc2NocmllYiBKaWF4aW5nIEh1Ogo+IFRoZSBSSzM1NzYgTlBVIGRvbWFpbnMgbmVl ZCBhIHNob3J0IHNldHRsZSB0aW1lIGFmdGVyIHRoZSBpZGxlCj4gcmVxdWVzdCBpcyByZWxlYXNl ZCBiZWZvcmUgdGhlIFFvUyByZWdpc3RlcnMgYmVoaW5kIHRoZSBkb21haW4gYXJlCj4gd3JpdHRl bjogcmVzdG9yaW5nIFFvUyBpbW1lZGlhdGVseSBhZnRlciBkZS1pZGxlIGNhbiByYWlzZSBhbiBT RXJyb3IKPiBvbiB0aGUgcmVnaXN0ZXIgYWNjZXNzIHdoaWxlIHRoZSBOb0MgaXMgc3RpbGwgc2V0 dGxpbmcgKG9ic2VydmVkIG9uCj4gUk9DSyA0RCBhcyBhIHBhbmljIGluc2lkZSByb2NrY2hpcF9w ZF9wb3dlcigpIGR1cmluZyBOUFUgcnVudGltZS1QTQo+IGN5Y2xpbmcpLgo+IAo+IFRoZSB2ZW5k b3Iga2VybmVsIGhhbmRsZXMgdGhpcyB3aXRoIGEgcGVyLWRvbWFpbiBkZWxheV91cyBmaWVsZAo+ IGFwcGxpZWQgYmV0d2VlbiB0aGUgZGUtaWRsZSByZXF1ZXN0IGFuZCB0aGUgUW9TIHJlc3RvcmUs IGNhcnJ5aW5nCj4gMTV1cyBmb3IgdGhlIFJLMzU3NiBOUFVUT1AgZG9tYWluLiAgTWlycm9yIHRo YXQ6IGFkZCBkZWxheV91cyB0bwo+IHJvY2tjaGlwX2RvbWFpbl9pbmZvLCBob25vciBpdCBpbiBy b2NrY2hpcF9wZF9wb3dlcigpIHJpZ2h0IGJlZm9yZQo+IHJvY2tjaGlwX3BtdV9yZXN0b3JlX3Fv cygpLCBhbmQgc2V0IDE1dXMgZm9yIE5QVVRPUCwgTlBVMCBhbmQgTlBVMQo+ICh0aGUgdHdvIGNv cmUgZG9tYWlucyBwb3dlci1jeWNsZSBjb25zdGFudGx5IHVuZGVyIHJ1bnRpbWUgUE0gYW5kCj4g c2hvd2VkIHRoZSBzYW1lIHN5bXB0b20gZHVyaW5nIGJyaW5nLXVwKS4gIEFsbCBvdGhlciBkb21h aW5zIGtlZXAgMCwKPiBzbyBub3RoaW5nIGNoYW5nZXMgZm9yIHRoZW0uCj4gCj4gU2lnbmVkLW9m Zi1ieTogSmlheGluZyBIdSA8Z2FoaW5nQGdhaGluZ3dvby5jb20+Cj4gLS0tCj4gIGRyaXZlcnMv cG1kb21haW4vcm9ja2NoaXAvcG0tZG9tYWlucy5jIHwgNTEgKysrKysrKysrKysrKystLS0tLS0t LS0tLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDI4IGluc2VydGlvbnMoKyksIDIzIGRlbGV0aW9ucygt KQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BtZG9tYWluL3JvY2tjaGlwL3BtLWRvbWFpbnMu YyBiL2RyaXZlcnMvcG1kb21haW4vcm9ja2NoaXAvcG0tZG9tYWlucy5jCj4gaW5kZXggNDkwYmJi MWQxLi4xNzg3ZjYyYmEgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9wbWRvbWFpbi9yb2NrY2hpcC9w bS1kb21haW5zLmMKPiArKysgYi9kcml2ZXJzL3BtZG9tYWluL3JvY2tjaGlwL3BtLWRvbWFpbnMu Ywo+IEBAIC01OSw2ICs1OSw3IEBAIHN0cnVjdCByb2NrY2hpcF9kb21haW5faW5mbyB7Cj4gIAl1 MzIgcHdyX29mZnNldDsKPiAgCXUzMiBtZW1fb2Zmc2V0Owo+ICAJdTMyIHJlcV9vZmZzZXQ7Cj4g Kwl1MzIgZGVsYXlfdXM7Cj4gIH07Cj4gIAo+ICBzdHJ1Y3Qgcm9ja2NoaXBfcG11X2luZm8gewo+ IEBAIC0xODUsNyArMTg2LDcgQEAgc3RydWN0IHJvY2tjaGlwX3BtdSB7Cj4gIAkubmVlZF9yZWd1 bGF0b3IgPSByZWd1bGF0b3IsCQkJXAo+ICB9Cj4gIAo+IC0jZGVmaW5lIERPTUFJTl9NX09fUl9H KF9uYW1lLCBwX29mZnNldCwgcHdyLCBzdGF0dXMsIG1fb2Zmc2V0LCBtX3N0YXR1cywgcl9zdGF0 dXMsIHJfb2Zmc2V0LCByZXEsIGlkbGUsIGFjaywgZ19tYXNrLCB3YWtldXApCVwKPiArI2RlZmlu ZSBET01BSU5fTV9PX1JfRyhfbmFtZSwgcF9vZmZzZXQsIHB3ciwgc3RhdHVzLCBtX29mZnNldCwg bV9zdGF0dXMsIHJfc3RhdHVzLCByX29mZnNldCwgcmVxLCBpZGxlLCBhY2ssIGdfbWFzaywgZGVs YXksIHdha2V1cCkJXAoKRE9NQUlOX01fT19SX0cgZGVzY3JpYmVzIHRoZSBmaWVsZHMgaXQgc2V0 cyAobWFzaywgb2Zmc2V0LCAgcmVndWxhdG9yIGNsay11bmdhdGUpCgpTbyBpZiB5b3UncmUgYWRk aW5nIHRoZSBuZXcgd2FrZXVwIGRlbGF5IHRoYXQgaXMgc3BlY2lmaWMgdG8gdGhpcyBvbmUKaW1w bGVtZW50YXRpb24tdmFyaWFudCwgcGxlYXNlIGFsc28gYWRkIGEgX1cgdGhlIG5hbWUgRE9NQUlO X01fT19SX0dfVwoKCk90aGVyd2lzZSBsb29rcyBnb29kLgoKCkhlaWtvCj4gIHsJCQkJCQkJXAo+ ICAJLm5hbWUgPSBfbmFtZSwJCQkJCVwKPiAgCS5wd3Jfb2Zmc2V0ID0gcF9vZmZzZXQsCQkJCVwK PiBAQCAtMjAwLDYgKzIwMSw3IEBAIHN0cnVjdCByb2NrY2hpcF9wbXUgewo+ICAJLnJlcV9tYXNr ID0gKHJlcSksCQkJCVwKPiAgCS5pZGxlX21hc2sgPSAoaWRsZSksCQkJCVwKPiAgCS5jbGtfdW5n YXRlX21hc2sgPSAoZ19tYXNrKSwJCQlcCj4gKwkuZGVsYXlfdXMgPSAoZGVsYXkpLAkJCQlcCj4g IAkuYWNrX21hc2sgPSAoYWNrKSwJCQkJXAo+ICAJLmFjdGl2ZV93YWtldXAgPSB3YWtldXAsCQkJ XAo+ICB9Cj4gQEAgLTI0NCw4ICsyNDYsOCBAQCBzdHJ1Y3Qgcm9ja2NoaXBfcG11IHsKPiAgI2Rl ZmluZSBET01BSU5fUkszNTY4KG5hbWUsIHB3ciwgcmVxLCB3YWtldXApCQlcCj4gIAlET01BSU5f TShuYW1lLCBwd3IsIHB3ciwgcmVxLCByZXEsIHJlcSwgd2FrZXVwKQo+ICAKPiAtI2RlZmluZSBE T01BSU5fUkszNTc2KG5hbWUsIHBfb2Zmc2V0LCBwd3IsIHN0YXR1cywgcl9zdGF0dXMsIHJfb2Zm c2V0LCByZXEsIGlkbGUsIGdfbWFzaywgd2FrZXVwKQlcCj4gLQlET01BSU5fTV9PX1JfRyhuYW1l LCBwX29mZnNldCwgcHdyLCBzdGF0dXMsIDAsIHJfc3RhdHVzLCByX3N0YXR1cywgcl9vZmZzZXQs IHJlcSwgaWRsZSwgaWRsZSwgZ19tYXNrLCB3YWtldXApCj4gKyNkZWZpbmUgRE9NQUlOX1JLMzU3 NihuYW1lLCBwX29mZnNldCwgcHdyLCBzdGF0dXMsIHJfc3RhdHVzLCByX29mZnNldCwgcmVxLCBp ZGxlLCBnX21hc2ssIGRlbGF5LCB3YWtldXApCVwKPiArCURPTUFJTl9NX09fUl9HKG5hbWUsIHBf b2Zmc2V0LCBwd3IsIHN0YXR1cywgMCwgcl9zdGF0dXMsIHJfc3RhdHVzLCByX29mZnNldCwgcmVx LCBpZGxlLCBpZGxlLCBnX21hc2ssIGRlbGF5LCB3YWtldXApCj4gIAo+ICAvKgo+ICAgKiBEeW5h bWljIE1lbW9yeSBDb250cm9sbGVyIG1heSBuZWVkIHRvIGNvb3JkaW5hdGUgd2l0aCB1cyAtLSBz ZWUKPiBAQCAtNjEyLDcgKzYxNCw2IEBAIHN0YXRpYyBpbnQgcm9ja2NoaXBfZG9fcG11X3NldF9w b3dlcl9kb21haW4oc3RydWN0IHJvY2tjaGlwX3BtX2RvbWFpbiAqcGQsCj4gIAkJCXJldHVybiBy ZXQ7Cj4gIAl9Cj4gIAo+IC0KPiAgCXJldCA9IHJlYWR4X3BvbGxfdGltZW91dF9hdG9taWMocm9j a2NoaXBfcG11X2RvbWFpbl9pc19vbiwgcGQsIGlzX29uLAo+ICAJCQkJCWlzX29uID09IG9uLCAw LCAxMDAwMCk7Cj4gIAlpZiAocmV0KSB7Cj4gQEAgLTY2Nyw2ICs2NjgsOSBAQCBzdGF0aWMgaW50 IHJvY2tjaGlwX3BkX3Bvd2VyKHN0cnVjdCByb2NrY2hpcF9wbV9kb21haW4gKnBkLCBib29sIHBv d2VyX29uKQo+ICAJCWlmIChyZXQgPCAwKQo+ICAJCQlnb3RvIG91dDsKPiAgCj4gKwkJaWYgKHBk LT5pbmZvLT5kZWxheV91cykKPiArCQkJdWRlbGF5KHBkLT5pbmZvLT5kZWxheV91cyk7Cj4gKwo+ ICAJCXJvY2tjaGlwX3BtdV9yZXN0b3JlX3FvcyhwZCk7Cj4gIAl9Cj4gIAo+IEBAIC0xMjg2LDI1 ICsxMjkwLDI2IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgcm9ja2NoaXBfZG9tYWluX2luZm8gcmsz NTY4X3BtX2RvbWFpbnNbXSA9IHsKPiAgfTsKPiAgCj4gIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgcm9j a2NoaXBfZG9tYWluX2luZm8gcmszNTc2X3BtX2RvbWFpbnNbXSA9IHsKPiAtCVtSSzM1NzZfUERf TlBVXQkJPSBET01BSU5fUkszNTc2KCJucHUiLCAgICAweDAsIEJJVCgwKSwgIEJJVCgwKSwgMCwg ICAgICAgMHgwLCAwLCAgICAgICAwLCAgICAgICAwLCAgICAgICBmYWxzZSksCj4gLQlbUkszNTc2 X1BEX05WTV0JCT0gRE9NQUlOX1JLMzU3NigibnZtIiwgICAgMHgwLCBCSVQoNiksICAwLCAgICAg IEJJVCg2KSwgIDB4NCwgQklUKDIpLCAgQklUKDE4KSwgQklUKDIpLCAgZmFsc2UpLAo+IC0JW1JL MzU3Nl9QRF9TREdNQUNdCT0gRE9NQUlOX1JLMzU3Nigic2RnbWFjIiwgMHgwLCBCSVQoNyksICAw LCAgICAgIEJJVCg3KSwgIDB4NCwgQklUKDEpLCAgQklUKDE3KSwgMHg2LCAgICAgZmFsc2UpLAo+ IC0JW1JLMzU3Nl9QRF9BVURJT10JPSBET01BSU5fUkszNTc2KCJhdWRpbyIsICAweDAsIEJJVCg4 KSwgIDAsICAgICAgQklUKDgpLCAgMHg0LCBCSVQoMCksICBCSVQoMTYpLCBCSVQoMCksICBmYWxz ZSksCj4gLQlbUkszNTc2X1BEX1BIUF0JCT0gRE9NQUlOX1JLMzU3NigicGhwIiwgICAgMHgwLCBC SVQoOSksICAwLCAgICAgIEJJVCg5KSwgIDB4MCwgQklUKDE1KSwgQklUKDE1KSwgQklUKDE1KSwg ZmFsc2UpLAo+IC0JW1JLMzU3Nl9QRF9TVUJQSFBdCT0gRE9NQUlOX1JLMzU3Nigic3VicGhwIiwg MHgwLCBCSVQoMTApLCAwLCAgICAgIEJJVCgxMCksIDB4MCwgMCwgICAgICAgMCwgICAgICAgMCwg ICAgICAgZmFsc2UpLAo+IC0JW1JLMzU3Nl9QRF9WT1BdCQk9IERPTUFJTl9SSzM1NzYoInZvcCIs ICAgIDB4MCwgQklUKDExKSwgMCwgICAgICBCSVQoMTEpLCAweDAsIDB4NjAwMCwgIDB4NjAwMCwg IDB4NjAwMCwgIGZhbHNlKSwKPiAtCVtSSzM1NzZfUERfVk8xXQkJPSBET01BSU5fUkszNTc2KCJ2 bzEiLCAgICAweDAsIEJJVCgxNCksIDAsICAgICAgQklUKDE0KSwgMHgwLCBCSVQoMTIpLCBCSVQo MTIpLCAweDcwMDAsICBmYWxzZSksCj4gLQlbUkszNTc2X1BEX1ZPMF0JCT0gRE9NQUlOX1JLMzU3 Nigidm8wIiwgICAgMHgwLCBCSVQoMTUpLCAwLCAgICAgIEJJVCgxNSksIDB4MCwgQklUKDExKSwg QklUKDExKSwgMHg2ODAwLCAgZmFsc2UpLAo+IC0JW1JLMzU3Nl9QRF9VU0JdCQk9IERPTUFJTl9S SzM1NzYoInVzYiIsICAgIDB4NCwgQklUKDApLCAgMCwgICAgICBCSVQoMTYpLCAweDAsIEJJVCgx MCksIEJJVCgxMCksIDB4NjQwMCwgIHRydWUpLAo+IC0JW1JLMzU3Nl9QRF9WSV0JCT0gRE9NQUlO X1JLMzU3NigidmkiLCAgICAgMHg0LCBCSVQoMSksICAwLCAgICAgIEJJVCgxNyksIDB4MCwgQklU KDkpLCAgQklUKDkpLCAgQklUKDkpLCAgZmFsc2UpLAo+IC0JW1JLMzU3Nl9QRF9WRVBVMF0JPSBE T01BSU5fUkszNTc2KCJ2ZXB1MCIsICAweDQsIEJJVCgyKSwgIDAsICAgICAgQklUKDE4KSwgMHgw LCBCSVQoNyksICBCSVQoNyksICAweDI4MCwgICBmYWxzZSksCj4gLQlbUkszNTc2X1BEX1ZFUFUx XQk9IERPTUFJTl9SSzM1NzYoInZlcHUxIiwgIDB4NCwgQklUKDMpLCAgMCwgICAgICBCSVQoMTkp LCAweDAsIEJJVCg4KSwgIEJJVCg4KSwgIEJJVCg4KSwgIGZhbHNlKSwKPiAtCVtSSzM1NzZfUERf VkRFQ10JPSBET01BSU5fUkszNTc2KCJ2ZGVjIiwgICAweDQsIEJJVCg0KSwgIDAsICAgICAgQklU KDIwKSwgMHgwLCBCSVQoNiksICBCSVQoNiksICBCSVQoNiksICBmYWxzZSksCj4gLQlbUkszNTc2 X1BEX1ZQVV0JCT0gRE9NQUlOX1JLMzU3NigidnB1IiwgICAgMHg0LCBCSVQoNSksICAwLCAgICAg IEJJVCgyMSksIDB4MCwgQklUKDUpLCAgQklUKDUpLCAgQklUKDUpLCAgZmFsc2UpLAo+IC0JW1JL MzU3Nl9QRF9OUFVUT1BdCT0gRE9NQUlOX1JLMzU3NigibnB1dG9wIiwgMHg0LCBCSVQoNiksICAw LCAgICAgIEJJVCgyMiksIDB4MCwgMHgxOCwgICAgMHgxOCwgICAgMHgxOCwgICAgZmFsc2UpLAo+ IC0JW1JLMzU3Nl9QRF9OUFUwXQk9IERPTUFJTl9SSzM1NzYoIm5wdTAiLCAgIDB4NCwgQklUKDcp LCAgMCwgICAgICBCSVQoMjMpLCAweDAsIEJJVCgxKSwgIEJJVCgxKSwgIDB4MWEsICAgIGZhbHNl KSwKPiAtCVtSSzM1NzZfUERfTlBVMV0JPSBET01BSU5fUkszNTc2KCJucHUxIiwgICAweDQsIEJJ VCg4KSwgIDAsICAgICAgQklUKDI0KSwgMHgwLCBCSVQoMiksICBCSVQoMiksICAweDFjLCAgICBm YWxzZSksCj4gLQlbUkszNTc2X1BEX0dQVV0JCT0gRE9NQUlOX1JLMzU3NigiZ3B1IiwgICAgMHg0 LCBCSVQoOSksICAwLCAgICAgIEJJVCgyNSksIDB4MCwgQklUKDApLCAgQklUKDApLCAgQklUKDAp LCAgZmFsc2UpLAo+ICsJLyogICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIG5hbWUgICAgcF9vZmZzZXQgcHdyICAgICAgc3RhdHVzICByX3N0YXR1cyByX29mZnNl dCByZXEgICAgICBpZGxlICAgICBnX21hc2sgICBkZWxheSB3YWtldXAgKi8KPiArCVtSSzM1NzZf UERfTlBVXQkJPSBET01BSU5fUkszNTc2KCJucHUiLCAgICAweDAsIEJJVCgwKSwgIEJJVCgwKSwg MCwgICAgICAgMHgwLCAwLCAgICAgICAwLCAgICAgICAwLCAgICAgICAwLCAgICBmYWxzZSksCj4g KwlbUkszNTc2X1BEX05WTV0JCT0gRE9NQUlOX1JLMzU3NigibnZtIiwgICAgMHgwLCBCSVQoNiks ICAwLCAgICAgIEJJVCg2KSwgIDB4NCwgQklUKDIpLCAgQklUKDE4KSwgQklUKDIpLCAgMCwgICAg ZmFsc2UpLAo+ICsJW1JLMzU3Nl9QRF9TREdNQUNdCT0gRE9NQUlOX1JLMzU3Nigic2RnbWFjIiwg MHgwLCBCSVQoNyksICAwLCAgICAgIEJJVCg3KSwgIDB4NCwgQklUKDEpLCAgQklUKDE3KSwgMHg2 LCAgICAgMCwgICAgZmFsc2UpLAo+ICsJW1JLMzU3Nl9QRF9BVURJT10JPSBET01BSU5fUkszNTc2 KCJhdWRpbyIsICAweDAsIEJJVCg4KSwgIDAsICAgICAgQklUKDgpLCAgMHg0LCBCSVQoMCksICBC SVQoMTYpLCBCSVQoMCksICAwLCAgICBmYWxzZSksCj4gKwlbUkszNTc2X1BEX1BIUF0JCT0gRE9N QUlOX1JLMzU3NigicGhwIiwgICAgMHgwLCBCSVQoOSksICAwLCAgICAgIEJJVCg5KSwgIDB4MCwg QklUKDE1KSwgQklUKDE1KSwgQklUKDE1KSwgMCwgICAgZmFsc2UpLAo+ICsJW1JLMzU3Nl9QRF9T VUJQSFBdCT0gRE9NQUlOX1JLMzU3Nigic3VicGhwIiwgMHgwLCBCSVQoMTApLCAwLCAgICAgIEJJ VCgxMCksIDB4MCwgMCwgICAgICAgMCwgICAgICAgMCwgICAgICAgMCwgICAgZmFsc2UpLAo+ICsJ W1JLMzU3Nl9QRF9WT1BdCQk9IERPTUFJTl9SSzM1NzYoInZvcCIsICAgIDB4MCwgQklUKDExKSwg MCwgICAgICBCSVQoMTEpLCAweDAsIDB4NjAwMCwgIDB4NjAwMCwgIDB4NjAwMCwgIDAsICAgIGZh bHNlKSwKPiArCVtSSzM1NzZfUERfVk8xXQkJPSBET01BSU5fUkszNTc2KCJ2bzEiLCAgICAweDAs IEJJVCgxNCksIDAsICAgICAgQklUKDE0KSwgMHgwLCBCSVQoMTIpLCBCSVQoMTIpLCAweDcwMDAs ICAwLCAgICBmYWxzZSksCj4gKwlbUkszNTc2X1BEX1ZPMF0JCT0gRE9NQUlOX1JLMzU3Nigidm8w IiwgICAgMHgwLCBCSVQoMTUpLCAwLCAgICAgIEJJVCgxNSksIDB4MCwgQklUKDExKSwgQklUKDEx KSwgMHg2ODAwLCAgMCwgICAgZmFsc2UpLAo+ICsJW1JLMzU3Nl9QRF9VU0JdCQk9IERPTUFJTl9S SzM1NzYoInVzYiIsICAgIDB4NCwgQklUKDApLCAgMCwgICAgICBCSVQoMTYpLCAweDAsIEJJVCgx MCksIEJJVCgxMCksIDB4NjQwMCwgIDAsICAgIHRydWUpLAo+ICsJW1JLMzU3Nl9QRF9WSV0JCT0g RE9NQUlOX1JLMzU3NigidmkiLCAgICAgMHg0LCBCSVQoMSksICAwLCAgICAgIEJJVCgxNyksIDB4 MCwgQklUKDkpLCAgQklUKDkpLCAgQklUKDkpLCAgMCwgICAgZmFsc2UpLAo+ICsJW1JLMzU3Nl9Q RF9WRVBVMF0JPSBET01BSU5fUkszNTc2KCJ2ZXB1MCIsICAweDQsIEJJVCgyKSwgIDAsICAgICAg QklUKDE4KSwgMHgwLCBCSVQoNyksICBCSVQoNyksICAweDI4MCwgICAwLCAgICBmYWxzZSksCj4g KwlbUkszNTc2X1BEX1ZFUFUxXQk9IERPTUFJTl9SSzM1NzYoInZlcHUxIiwgIDB4NCwgQklUKDMp LCAgMCwgICAgICBCSVQoMTkpLCAweDAsIEJJVCg4KSwgIEJJVCg4KSwgIEJJVCg4KSwgIDAsICAg IGZhbHNlKSwKPiArCVtSSzM1NzZfUERfVkRFQ10JPSBET01BSU5fUkszNTc2KCJ2ZGVjIiwgICAw eDQsIEJJVCg0KSwgIDAsICAgICAgQklUKDIwKSwgMHgwLCBCSVQoNiksICBCSVQoNiksICBCSVQo NiksICAwLCAgICBmYWxzZSksCj4gKwlbUkszNTc2X1BEX1ZQVV0JCT0gRE9NQUlOX1JLMzU3Nigi dnB1IiwgICAgMHg0LCBCSVQoNSksICAwLCAgICAgIEJJVCgyMSksIDB4MCwgQklUKDUpLCAgQklU KDUpLCAgQklUKDUpLCAgMCwgICAgZmFsc2UpLAo+ICsJW1JLMzU3Nl9QRF9OUFVUT1BdCT0gRE9N QUlOX1JLMzU3NigibnB1dG9wIiwgMHg0LCBCSVQoNiksICAwLCAgICAgIEJJVCgyMiksIDB4MCwg MHgxOCwgICAgMHgxOCwgICAgMHgxOCwgICAgMTUsICAgZmFsc2UpLAo+ICsJW1JLMzU3Nl9QRF9O UFUwXQk9IERPTUFJTl9SSzM1NzYoIm5wdTAiLCAgIDB4NCwgQklUKDcpLCAgMCwgICAgICBCSVQo MjMpLCAweDAsIEJJVCgxKSwgIEJJVCgxKSwgIDB4MWEsICAgIDE1LCAgIGZhbHNlKSwKPiArCVtS SzM1NzZfUERfTlBVMV0JPSBET01BSU5fUkszNTc2KCJucHUxIiwgICAweDQsIEJJVCg4KSwgIDAs ICAgICAgQklUKDI0KSwgMHgwLCBCSVQoMiksICBCSVQoMiksICAweDFjLCAgICAxNSwgICBmYWxz ZSksCj4gKwlbUkszNTc2X1BEX0dQVV0JCT0gRE9NQUlOX1JLMzU3NigiZ3B1IiwgICAgMHg0LCBC SVQoOSksICAwLCAgICAgIEJJVCgyNSksIDB4MCwgQklUKDApLCAgQklUKDApLCAgQklUKDApLCAg MCwgICAgZmFsc2UpLAo+ICB9Owo+ICAKPiAgc3RhdGljIGNvbnN0IHN0cnVjdCByb2NrY2hpcF9k b21haW5faW5mbyByazM1ODhfcG1fZG9tYWluc1tdID0gewo+IAoKCgoKCl9fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkxpbnV4LXJvY2tjaGlwIG1haWxpbmcg bGlzdApMaW51eC1yb2NrY2hpcEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZy YWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcm9ja2NoaXAK From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) 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dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=S/3Q0Bnq; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="S/3Q0Bnq" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=mABh2OQBhAUA7eN+87r478yGoqxajXeOENCfKZxWJeA=; b=S/3Q0Bnq4xPJ4O8no5JeqAx3On L9u7qtyvrLbPLK4sNmOsNDmzx9YGxap/s+dXIkE2DVu1ePPrSMnIV79P7QE9N5XcLzNxY09nJ3xCF rEEgJamiwBjfHBhSX9+f8Bz+22fl2aj3ZRymXrTXZIV2N+Thzq55RYVYtQhl50/RwmGEKqAe5Bhi9 qZ+EKCMhKWJ0nD4k4/RSkthYkuh2tL43W+0nlOMTkyxN9NjgW8j2PDHfREpLbzMmdW36IwtGhWVVG i/W+ZxBUrMtVlZieZ0H0WZJ/58Ih5M3OwisS3zcDQ/thjEONoREPev7ACzSt4YaVIO6oJmSsSWMJj FRPC5c7g==; From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: tomeu@tomeuvizoso.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, Jiaxing Hu Cc: chaoyi.chen@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: Re: [RFC PATCH v2 2/8] pmdomain/rockchip: add optional per-domain power-on settle delay Date: Wed, 29 Jul 2026 17:20:20 +0200 Message-ID: <3322194.D8ZAKjAxdT@diego> In-Reply-To: <20260718031146.3368811-3-gahing@gahingwoo.com> References: <20260718031146.3368811-1-gahing@gahingwoo.com> <20260718031146.3368811-3-gahing@gahingwoo.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Samstag, 18. Juli 2026, 05:11:40 Mitteleurop=C3=A4ische Sommerzeit schri= eb Jiaxing Hu: > The RK3576 NPU domains need a short settle time after the idle > request is released before the QoS registers behind the domain are > written: restoring QoS immediately after de-idle can raise an SError > on the register access while the NoC is still settling (observed on > ROCK 4D as a panic inside rockchip_pd_power() during NPU runtime-PM > cycling). >=20 > The vendor kernel handles this with a per-domain delay_us field > applied between the de-idle request and the QoS restore, carrying > 15us for the RK3576 NPUTOP domain. Mirror that: add delay_us to > rockchip_domain_info, honor it in rockchip_pd_power() right before > rockchip_pmu_restore_qos(), and set 15us for NPUTOP, NPU0 and NPU1 > (the two core domains power-cycle constantly under runtime PM and > showed the same symptom during bring-up). All other domains keep 0, > so nothing changes for them. >=20 > Signed-off-by: Jiaxing Hu > --- > drivers/pmdomain/rockchip/pm-domains.c | 51 ++++++++++++++------------ > 1 file changed, 28 insertions(+), 23 deletions(-) >=20 > diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/ro= ckchip/pm-domains.c > index 490bbb1d1..1787f62ba 100644 > --- a/drivers/pmdomain/rockchip/pm-domains.c > +++ b/drivers/pmdomain/rockchip/pm-domains.c > @@ -59,6 +59,7 @@ struct rockchip_domain_info { > u32 pwr_offset; > u32 mem_offset; > u32 req_offset; > + u32 delay_us; > }; > =20 > struct rockchip_pmu_info { > @@ -185,7 +186,7 @@ struct rockchip_pmu { > .need_regulator =3D regulator, \ > } > =20 > -#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status,= r_status, r_offset, req, idle, ack, g_mask, wakeup) \ > +#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status,= r_status, r_offset, req, idle, ack, g_mask, delay, wakeup) \ DOMAIN_M_O_R_G describes the fields it sets (mask, offset, regulator clk-u= ngate) So if you're adding the new wakeup delay that is specific to this one implementation-variant, please also add a _W the name DOMAIN_M_O_R_G_W Otherwise looks good. Heiko > { \ > .name =3D _name, \ > .pwr_offset =3D p_offset, \ > @@ -200,6 +201,7 @@ struct rockchip_pmu { > .req_mask =3D (req), \ > .idle_mask =3D (idle), \ > .clk_ungate_mask =3D (g_mask), \ > + .delay_us =3D (delay), \ > .ack_mask =3D (ack), \ > .active_wakeup =3D wakeup, \ > } > @@ -244,8 +246,8 @@ struct rockchip_pmu { > #define DOMAIN_RK3568(name, pwr, req, wakeup) \ > DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) > =20 > -#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, r= eq, idle, g_mask, wakeup) \ > - DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_of= fset, req, idle, idle, g_mask, wakeup) > +#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, r= eq, idle, g_mask, delay, wakeup) \ > + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_of= fset, req, idle, idle, g_mask, delay, wakeup) > =20 > /* > * Dynamic Memory Controller may need to coordinate with us -- see > @@ -612,7 +614,6 @@ static int rockchip_do_pmu_set_power_domain(struct ro= ckchip_pm_domain *pd, > return ret; > } > =20 > - > ret =3D readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, > is_on =3D=3D on, 0, 10000); > if (ret) { > @@ -667,6 +668,9 @@ static int rockchip_pd_power(struct rockchip_pm_domai= n *pd, bool power_on) > if (ret < 0) > goto out; > =20 > + if (pd->info->delay_us) > + udelay(pd->info->delay_us); > + > rockchip_pmu_restore_qos(pd); > } > =20 > @@ -1286,25 +1290,26 @@ static const struct rockchip_domain_info rk3568_p= m_domains[] =3D { > }; > =20 > static const struct rockchip_domain_info rk3576_pm_domains[] =3D { > - [RK3576_PD_NPU] =3D DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, = 0x0, 0, 0, 0, false), > - [RK3576_PD_NVM] =3D DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(= 6), 0x4, BIT(2), BIT(18), BIT(2), false), > - [RK3576_PD_SDGMAC] =3D DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BI= T(7), 0x4, BIT(1), BIT(17), 0x6, false), > - [RK3576_PD_AUDIO] =3D DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT= (8), 0x4, BIT(0), BIT(16), BIT(0), false), > - [RK3576_PD_PHP] =3D DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(= 9), 0x0, BIT(15), BIT(15), BIT(15), false), > - [RK3576_PD_SUBPHP] =3D DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BI= T(10), 0x0, 0, 0, 0, false), > - [RK3576_PD_VOP] =3D DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(= 11), 0x0, 0x6000, 0x6000, 0x6000, false), > - [RK3576_PD_VO1] =3D DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(= 14), 0x0, BIT(12), BIT(12), 0x7000, false), > - [RK3576_PD_VO0] =3D DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(= 15), 0x0, BIT(11), BIT(11), 0x6800, false), > - [RK3576_PD_USB] =3D DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(= 16), 0x0, BIT(10), BIT(10), 0x6400, true), > - [RK3576_PD_VI] =3D DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(1= 7), 0x0, BIT(9), BIT(9), BIT(9), false), > - [RK3576_PD_VEPU0] =3D DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT= (18), 0x0, BIT(7), BIT(7), 0x280, false), > - [RK3576_PD_VEPU1] =3D DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT= (19), 0x0, BIT(8), BIT(8), BIT(8), false), > - [RK3576_PD_VDEC] =3D DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(= 20), 0x0, BIT(6), BIT(6), BIT(6), false), > - [RK3576_PD_VPU] =3D DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(= 21), 0x0, BIT(5), BIT(5), BIT(5), false), > - [RK3576_PD_NPUTOP] =3D DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BI= T(22), 0x0, 0x18, 0x18, 0x18, false), > - [RK3576_PD_NPU0] =3D DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(= 23), 0x0, BIT(1), BIT(1), 0x1a, false), > - [RK3576_PD_NPU1] =3D DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(= 24), 0x0, BIT(2), BIT(2), 0x1c, false), > - [RK3576_PD_GPU] =3D DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(= 25), 0x0, BIT(0), BIT(0), BIT(0), false), > + /* name p_offset pwr = status r_status r_offset req idle g_mask delay wakeup */ > + [RK3576_PD_NPU] =3D DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, = 0x0, 0, 0, 0, 0, false), > + [RK3576_PD_NVM] =3D DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(= 6), 0x4, BIT(2), BIT(18), BIT(2), 0, false), > + [RK3576_PD_SDGMAC] =3D DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BI= T(7), 0x4, BIT(1), BIT(17), 0x6, 0, false), > + [RK3576_PD_AUDIO] =3D DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT= (8), 0x4, BIT(0), BIT(16), BIT(0), 0, false), > + [RK3576_PD_PHP] =3D DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(= 9), 0x0, BIT(15), BIT(15), BIT(15), 0, false), > + [RK3576_PD_SUBPHP] =3D DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BI= T(10), 0x0, 0, 0, 0, 0, false), > + [RK3576_PD_VOP] =3D DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(= 11), 0x0, 0x6000, 0x6000, 0x6000, 0, false), > + [RK3576_PD_VO1] =3D DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(= 14), 0x0, BIT(12), BIT(12), 0x7000, 0, false), > + [RK3576_PD_VO0] =3D DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(= 15), 0x0, BIT(11), BIT(11), 0x6800, 0, false), > + [RK3576_PD_USB] =3D DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(= 16), 0x0, BIT(10), BIT(10), 0x6400, 0, true), > + [RK3576_PD_VI] =3D DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(1= 7), 0x0, BIT(9), BIT(9), BIT(9), 0, false), > + [RK3576_PD_VEPU0] =3D DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT= (18), 0x0, BIT(7), BIT(7), 0x280, 0, false), > + [RK3576_PD_VEPU1] =3D DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT= (19), 0x0, BIT(8), BIT(8), BIT(8), 0, false), > + [RK3576_PD_VDEC] =3D DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(= 20), 0x0, BIT(6), BIT(6), BIT(6), 0, false), > + [RK3576_PD_VPU] =3D DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(= 21), 0x0, BIT(5), BIT(5), BIT(5), 0, false), > + [RK3576_PD_NPUTOP] =3D DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BI= T(22), 0x0, 0x18, 0x18, 0x18, 15, false), > + [RK3576_PD_NPU0] =3D DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(= 23), 0x0, BIT(1), BIT(1), 0x1a, 15, false), > + [RK3576_PD_NPU1] =3D DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(= 24), 0x0, BIT(2), BIT(2), 0x1c, 15, false), > + [RK3576_PD_GPU] =3D DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(= 25), 0x0, BIT(0), BIT(0), BIT(0), 0, false), > }; > =20 > static const struct rockchip_domain_info rk3588_pm_domains[] =3D { >=20