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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 10/26/23 12:18, Max Chou wrote: > Vector crypto spec defines the Zvkt extension that included all of the > instructions of Zvbb & Zvbc extensions and some vector instructions. > > Signed-off-by: Max Chou > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/cpu_cfg.h | 1 + > target/riscv/tcg/tcg-cpu.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index e7ce977189c..d8d17dedeed 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -94,6 +94,7 @@ struct RISCVCPUConfig { > bool ext_zvknhb; > bool ext_zvksed; > bool ext_zvksh; > + bool ext_zvkt; > bool ext_zmmul; > bool ext_zvfbfmin; > bool ext_zvfbfwma; > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index c5ff03efce9..b9eaecb699c 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -499,6 +499,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > + if (cpu->cfg.ext_zvkt) { > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); > + } > + > /* > * In principle Zve*x would also suffice here, were they supported > * in qemu