From mboxrd@z Thu Jan 1 00:00:00 1970 From: arnd@arndb.de (Arnd Bergmann) Date: Thu, 18 Feb 2016 17:27:48 +0100 Subject: [PATCH v2] irqchip: irq-mvebu-odmi: new driver for platform MSI on Marvell 7K/8K In-Reply-To: <20160218171623.664dabd1@free-electrons.com> References: <1455811134-3679-1-git-send-email-thomas.petazzoni@free-electrons.com> <3923904.c50oLNXXZ1@wuerfel> <20160218171623.664dabd1@free-electrons.com> Message-ID: <3474575.KNRGuJK4d6@wuerfel> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thursday 18 February 2016 17:16:23 Thomas Petazzoni wrote: > > On Thu, 18 Feb 2016 17:08:05 +0100, Arnd Bergmann wrote: > > On Thursday 18 February 2016 16:58:54 Thomas Petazzoni wrote: > > > +- marvell,spi-base : List of GIC base SPI interrupts, one for each > > > + ODMI frame. Those SPI interrupts are 0-based, > > > + i.e marvell,spi-base = <128> will use SPI #96. > > > + See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt > > > + for details about the GIC Device Tree binding. > > > > > > > Why are these not just in an 'interrupts' property as we do for other > > nested irqchips? > > I modeled this after the GICv2m bindings. I think the reason is that if > we were to use the interrupts property, we should be listing *all* > interrupts of the parent interrupt controller we are using. Which would > be quite painful when your ODMI interrupt controller uses 32 interrupts > of the parent controller (I think for the GICv2m, it's even more). > > I.e, we currently say: > > marvell,spi-base = <128>, <136>, <144>, <152> > > but in fact we are using 128, 129, 130, 131, 132, 133, 134, 135, 136, > 137, etc. until 159. > > If you think > > interrupts = <128>, <136>, <144>, <152> > > is still correct, then why not. But I believe this might be confusing, > as people will think that we are only using interrupts 128, 136, 144 > and 152, and not 129, 133, 147 or 158. > Ok, got it. Your current version seems fine then. Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1946915AbcBRQ2j (ORCPT ); Thu, 18 Feb 2016 11:28:39 -0500 Received: from mout.kundenserver.de ([217.72.192.73]:49434 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1425080AbcBRQ2i (ORCPT ); Thu, 18 Feb 2016 11:28:38 -0500 From: Arnd Bergmann To: Thomas Petazzoni Cc: linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Lior Amsalem , Andrew Lunn , Nadav Haklai , Gregory Clement , Sebastian Hesselbarth Subject: Re: [PATCH v2] irqchip: irq-mvebu-odmi: new driver for platform MSI on Marvell 7K/8K Date: Thu, 18 Feb 2016 17:27:48 +0100 Message-ID: <3474575.KNRGuJK4d6@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <20160218171623.664dabd1@free-electrons.com> References: <1455811134-3679-1-git-send-email-thomas.petazzoni@free-electrons.com> <3923904.c50oLNXXZ1@wuerfel> <20160218171623.664dabd1@free-electrons.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:Jlg4lVWnQSQZ+JLEePSY3ms3/4F/icG/cDXpG6OjeLzVI3Ia2GH F1vjlR6P1lwudH5JfjJRUpInKniEep+Dap886DsN4A4BID8j7C45Ag+BlRAzb5Lk+yNVUjm YYy2Bc2BueQ1HoCbFLckJVYoBlB/GQ7sMV6RdvwRL3HdXDYvMOGlqhOg06sQHkmbW7ijqfn 2UNaj+hbXCsEBNHaXGS4g== X-UI-Out-Filterresults: notjunk:1;V01:K0:jZ+NJ+AgQrA=:tsaE8o2imEf9FaE0pO7KHd 8rD1zctm3Rk3ldA/jitt4sH8b6svnIq+eEGwzxTzWIuVxKqG2WLEoJlOJxbeb6xrn5WrDF3cp Ss+BLkSAfV68IKJRaJyGnsi3SDIu+mOt8sHZQYhVQSFEtZDAuienmv+zdiksyJJYkQj+/evv8 1JawewfeLrBe4Kv2oAsQ/ivQiqewRwBw+Bb8Y8Fsqdb2lMm+kviT6oJD1Pyg/ZGanE6ohgv4C pLDz2WvXr/p7gH7eDRLfmQL+WBJZouEteZYW3+jz4YfpSSXzBC7vHdQpKueilel86HE8ZLiA/ ZywPbpJm4da2oT53DPuweMaoUILyhj0qHnjAVtrk4Zx1yUBGP903iilvgr7JvywOs5630gyUu kcQLKRGqpSa21dnacCNmT2PSQK+juQ/f26JbbLWR+9OBQPIaobRCnVapHtEaxzyWgIN2mKXTV JD2S/jRcn8s6CF7mloXXG82heczeaEi79wuqsRlJT4PO62CseJeGJPnC0iprLIMQx3+VLXmkP DFp4+tl6TmRWCb4Mr343q2AQpu09CGAGtzWl8Oi+8daD67QVBah/1AhVh09czmu7zU2tkCqXw F5WLnHOFYLy1ePzB6/nqNDBFII4iYh/7Jk6MJEb+0vV6ZBWAJQALRasvf4j2WlfkuSkbXQE8Z 9c09lQlkUgzA2SwNuCIoB86ikdp2EGxQn+vAtSMvruUfB8NOqKL7Q33iq/DfRAGUiPEtIWhD+ Fmy77+8AKdvC716P Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday 18 February 2016 17:16:23 Thomas Petazzoni wrote: > > On Thu, 18 Feb 2016 17:08:05 +0100, Arnd Bergmann wrote: > > On Thursday 18 February 2016 16:58:54 Thomas Petazzoni wrote: > > > +- marvell,spi-base : List of GIC base SPI interrupts, one for each > > > + ODMI frame. Those SPI interrupts are 0-based, > > > + i.e marvell,spi-base = <128> will use SPI #96. > > > + See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt > > > + for details about the GIC Device Tree binding. > > > > > > > Why are these not just in an 'interrupts' property as we do for other > > nested irqchips? > > I modeled this after the GICv2m bindings. I think the reason is that if > we were to use the interrupts property, we should be listing *all* > interrupts of the parent interrupt controller we are using. Which would > be quite painful when your ODMI interrupt controller uses 32 interrupts > of the parent controller (I think for the GICv2m, it's even more). > > I.e, we currently say: > > marvell,spi-base = <128>, <136>, <144>, <152> > > but in fact we are using 128, 129, 130, 131, 132, 133, 134, 135, 136, > 137, etc. until 159. > > If you think > > interrupts = <128>, <136>, <144>, <152> > > is still correct, then why not. But I believe this might be confusing, > as people will think that we are only using interrupts 128, 136, 144 > and 152, and not 129, 133, 147 or 158. > Ok, got it. Your current version seems fine then. Arnd