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From: Michael Richardson <mcr@sandelman.ca>
To: Zev Weiss <zweiss@equinix.com>
Cc: "openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>
Subject: Re: Aspeed SuperIO runtime management
Date: Wed, 04 Oct 2023 10:02:20 -0400	[thread overview]
Message-ID: <3490.1696428140@localhost> (raw)
In-Reply-To: <20231004003427.GI19997@packtop>

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Zev Weiss <zweiss@equinix.com> wrote:
    > For reasons I don't fully understand but that I think are orthogonal to
    > this particular issue, the platform in question can't use the Aspeed
    > VUART, and so instead uses two SUARTs configured back-to-back via the
    > UART mux to provide the host's serial console.  The host's firmware thus
    > enables its UART early in the host boot sequence, which requires that
    > the AST2500's built-in SuperIO device be enabled (SCU70[20]=0).

I don't really understand much about these SUARTs and the SuperIO.

I guess the SuperIO is supposed to now be provisioned only by the BMC,
except for this exception.
I use the word provisioned here, because I think that the host would get to
configure the UARTs speed, stop bits, etc. via it's normal process.

My question is: what if the BMC just did all the provisioning necessary and
the host either just didn't, or perhaps if it really wants to do this, that
it be faked into writing to some other thing that isn't really those
registers.

    > 1. Does anyone know of any better ways of handling this problem?



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  reply	other threads:[~2023-10-04 14:09 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-04  0:34 Aspeed SuperIO runtime management Zev Weiss
2023-10-04 14:02 ` Michael Richardson [this message]
2023-10-04 22:55   ` Andrew Jeffery
2023-10-04 22:52 ` Andrew Jeffery
2023-10-17  1:55   ` Zev Weiss

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