diff for duplicates of <3497055.MjziMiDfL7@diego> diff --git a/a/1.txt b/N1/1.txt index 4204f90..7c19db2 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -108,7 +108,7 @@ depending on what the real board is labeled > +&i2c1 { > + status = "okay"; > + -> + hym8563: hym8563@51 { +> + hym8563: hym8563 at 51 { > + compatible = "haoyu,hym8563"; > + reg = <0x51>; > + #clock-cells = <0>; @@ -176,9 +176,9 @@ missing newline as stated above in general, please sort nodes by register address, so for example - interrupt-controller@10139000 + interrupt-controller at 10139000 should be before - clock-controller@20000000 + clock-controller at 20000000 same for all other nodes @@ -229,7 +229,7 @@ accepted > + -> + cpu0: cpu@f00 { +> + cpu0: cpu at f00 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf00>; @@ -247,7 +247,7 @@ for now > + clocks = <&cru ARMCLK>; > + resets = <&cru SRST_CORE0>; > + }; -> + cpu1: cpu@f01 { +> + cpu1: cpu at f01 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf01>; @@ -261,7 +261,7 @@ for now > + #size-cells = <1>; > + ranges; > + -> + pdma: pdma@20078000 { +> + pdma: pdma at 20078000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0x20078000 0x4000>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -294,7 +294,7 @@ IRQ_TYPE_LEVEL_HIGH)>, > + clock-frequency = <24000000>; > + }; > + -> + cru: clock-controller@20000000 { +> + cru: clock-controller at 20000000 { > + compatible = "rockchip,rk3036-cru"; > + reg = <0x20000000 0x1000>; > + rockchip,grf = <&grf>; @@ -304,7 +304,7 @@ IRQ_TYPE_LEVEL_HIGH)>, > + assigned-clock-rates = <594000000>; > + }; > + -> + uart0: serial@20060000 { +> + uart0: serial at 20060000 { > + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; > + reg = <0x20060000 0x100>; > + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; @@ -327,7 +327,7 @@ not everybody will want to use uart0 ... same is true for the other two uarts. > + }; > + -> + uart1: serial@20064000 { +> + uart1: serial at 20064000 { > + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; > + reg = <0x20064000 0x100>; > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; @@ -340,7 +340,7 @@ not everybody will want to use uart0 ... same is true for the other two uarts. > + pinctrl-0 = <&uart1_xfer>; > + }; > + -> + uart2: serial@20068000 { +> + uart2: serial at 20068000 { > + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; > + reg = <0x20068000 0x100>; > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -353,7 +353,7 @@ not everybody will want to use uart0 ... same is true for the other two uarts. > + pinctrl-0 = <&uart2_xfer>; > + }; > + -> + pwm0: pwm@20050000 { +> + pwm0: pwm at 20050000 { > + compatible = "rockchip,rk2928-pwm"; compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; @@ -370,7 +370,7 @@ pwm in the driver without needing to change the dts > + status = "disabled"; > + }; > + -> + pwm1: pwm@20050010 { +> + pwm1: pwm at 20050010 { > + compatible = "rockchip,rk2928-pwm"; > + reg = <0x20050010 0x10>; > + #pwm-cells = <3>; @@ -381,7 +381,7 @@ pwm in the driver without needing to change the dts > + status = "disabled"; > + }; > + -> + pwm2: pwm@20050020 { +> + pwm2: pwm at 20050020 { > + compatible = "rockchip,rk2928-pwm"; > + reg = <0x20050020 0x10>; > + #pwm-cells = <3>; @@ -392,7 +392,7 @@ pwm in the driver without needing to change the dts > + status = "disabled"; > + }; > + -> + pwm3: pwm@20050030 { +> + pwm3: pwm at 20050030 { > + compatible = "rockchip,rk2928-pwm"; > + reg = <0x20050030 0x10>; > + #pwm-cells = <2>; @@ -403,12 +403,12 @@ pwm in the driver without needing to change the dts > + status = "disabled"; > + }; > + -> + sram: sram@10080000 { +> + sram: sram at 10080000 { > + compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; > + reg = <0x10080000 0x2000>; > + }; > + -> + gic: interrupt-controller@10139000 { +> + gic: interrupt-controller at 10139000 { > + compatible = "arm,gic-400"; > + interrupt-controller; > + #interrupt-cells = <3>; @@ -421,7 +421,7 @@ pwm in the driver without needing to change the dts > + interrupts = <GIC_PPI 9 0xf04>; > + }; > + -> + grf: syscon@20008000 { +> + grf: syscon at 20008000 { > + compatible = "rockchip,rk3036-grf", "syscon"; > + reg = <0x20008000 0x1000>; > + }; @@ -433,7 +433,7 @@ pwm in the driver without needing to change the dts > + #size-cells = <1>; > + ranges; > + -> + gpio0: gpio0@2007c000 { +> + gpio0: gpio0 at 2007c000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x2007c000 0x100>; > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; @@ -446,7 +446,7 @@ pwm in the driver without needing to change the dts > + #interrupt-cells = <2>; > + }; > + -> + gpio1: gpio1@20080000 { +> + gpio1: gpio1 at 20080000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x20080000 0x100>; > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -459,7 +459,7 @@ pwm in the driver without needing to change the dts > + #interrupt-cells = <2>; > + }; > + -> + gpio2: gpio2@20084000 { +> + gpio2: gpio2 at 20084000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x20084000 0x100>; > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -559,7 +559,7 @@ tabs please > + }; > + }; > + -> + i2c1: i2c@20056000 { +> + i2c1: i2c at 20056000 { > + compatible = "rockchip,rk3288-i2c"; > + reg = <0x20056000 0x1000>; > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N1/content_digest index ed59595..ac76e83 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,19 +1,9 @@ "ref\01442478540-15068-1-git-send-email-zhengxing@rock-chips.com\0" "ref\01442478540-15068-2-git-send-email-zhengxing@rock-chips.com\0" - "From\0Heiko St\303\274bner <heiko@sntech.de>\0" - "Subject\0Re: [PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts\0" + "From\0heiko@sntech.de (Heiko St\303\274bner)\0" + "Subject\0[PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts\0" "Date\0Thu, 17 Sep 2015 11:18:53 +0200\0" - "To\0Xing Zheng <zhengxing@rock-chips.com>\0" - "Cc\0linux-rockchip@lists.infradead.org" - Rob Herring <robh+dt@kernel.org> - Pawel Moll <pawel.moll@arm.com> - Mark Rutland <mark.rutland@arm.com> - Ian Campbell <ijc+devicetree@hellion.org.uk> - Kumar Gala <galak@codeaurora.org> - Russell King <linux@arm.linux.org.uk> - devicetree@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Am Donnerstag, 17. September 2015, 16:28:52 schrieb Xing Zheng:\n" @@ -126,7 +116,7 @@ "> +&i2c1 {\n" "> +\tstatus = \"okay\";\n" "> +\n" - "> + hym8563: hym8563@51 {\n" + "> + hym8563: hym8563 at 51 {\n" "> +\t\tcompatible = \"haoyu,hym8563\";\n" "> +\t\treg = <0x51>;\n" "> +\t\t#clock-cells = <0>;\n" @@ -194,9 +184,9 @@ "\n" "in general, please sort nodes by register address, so for example\n" "\n" - "\tinterrupt-controller@10139000\n" + "\tinterrupt-controller at 10139000\n" "should be before\n" - "\tclock-controller@20000000\n" + "\tclock-controller at 20000000\n" "\n" "same for all other nodes\n" "\n" @@ -247,7 +237,7 @@ "\n" "\n" "> +\n" - "> +\t\tcpu0: cpu@f00 {\n" + "> +\t\tcpu0: cpu at f00 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\treg = <0xf00>;\n" @@ -265,7 +255,7 @@ "> +\t\t\tclocks = <&cru ARMCLK>;\n" "> +\t\t\tresets = <&cru SRST_CORE0>;\n" "> +\t\t};\n" - "> +\t\tcpu1: cpu@f01 {\n" + "> +\t\tcpu1: cpu at f01 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\treg = <0xf01>;\n" @@ -279,7 +269,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> + pdma: pdma@20078000 {\n" + "> + pdma: pdma at 20078000 {\n" "> + compatible = \"arm,pl330\", \"arm,primecell\";\n" "> + reg = <0x20078000 0x4000>;\n" "> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -312,7 +302,7 @@ "> +\t\tclock-frequency = <24000000>;\n" "> +\t};\n" "> +\n" - "> +\tcru: clock-controller@20000000 {\n" + "> +\tcru: clock-controller at 20000000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-cru\";\n" "> +\t\treg = <0x20000000 0x1000>;\n" "> +\t\trockchip,grf = <&grf>;\n" @@ -322,7 +312,7 @@ "> +\t\tassigned-clock-rates = <594000000>;\n" "> +\t};\n" "> +\n" - "> +\tuart0: serial@20060000 {\n" + "> +\tuart0: serial at 20060000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-uart\", \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x20060000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -345,7 +335,7 @@ "\n" "> +\t};\n" "> +\n" - "> +\tuart1: serial@20064000 {\n" + "> +\tuart1: serial at 20064000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-uart\", \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x20064000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -358,7 +348,7 @@ "> +\t\tpinctrl-0 = <&uart1_xfer>;\n" "> +\t};\n" "> +\n" - "> +\tuart2: serial@20068000 {\n" + "> +\tuart2: serial at 20068000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-uart\", \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x20068000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -371,7 +361,7 @@ "> +\t\tpinctrl-0 = <&uart2_xfer>;\n" "> +\t};\n" "> +\n" - "> +\tpwm0: pwm@20050000 {\n" + "> +\tpwm0: pwm at 20050000 {\n" "> +\t\tcompatible = \"rockchip,rk2928-pwm\";\n" "\n" "\t\tcompatible = \"rockchip,rk3036-pwm\", \"rockchip,rk2928-pwm\";\n" @@ -388,7 +378,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tpwm1: pwm@20050010 {\n" + "> +\tpwm1: pwm at 20050010 {\n" "> +\t\tcompatible = \"rockchip,rk2928-pwm\";\n" "> +\t\treg = <0x20050010 0x10>;\n" "> +\t\t#pwm-cells = <3>;\n" @@ -399,7 +389,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tpwm2: pwm@20050020 {\n" + "> +\tpwm2: pwm at 20050020 {\n" "> +\t\tcompatible = \"rockchip,rk2928-pwm\";\n" "> +\t\treg = <0x20050020 0x10>;\n" "> +\t\t#pwm-cells = <3>;\n" @@ -410,7 +400,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tpwm3: pwm@20050030 {\n" + "> +\tpwm3: pwm at 20050030 {\n" "> +\t\tcompatible = \"rockchip,rk2928-pwm\";\n" "> +\t\treg = <0x20050030 0x10>;\n" "> +\t\t#pwm-cells = <2>;\n" @@ -421,12 +411,12 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tsram: sram@10080000 {\n" + "> +\tsram: sram at 10080000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-smp-sram\", \"mmio-sram\";\n" "> +\t\treg = <0x10080000 0x2000>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller@10139000 {\n" + "> +\tgic: interrupt-controller at 10139000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\tinterrupt-controller;\n" "> +\t\t#interrupt-cells = <3>;\n" @@ -439,7 +429,7 @@ "> +\t\tinterrupts = <GIC_PPI 9 0xf04>;\n" "> +\t};\n" "> +\n" - "> +\tgrf: syscon@20008000 {\n" + "> +\tgrf: syscon at 20008000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-grf\", \"syscon\";\n" "> +\t\treg = <0x20008000 0x1000>;\n" "> +\t};\n" @@ -451,7 +441,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tgpio0: gpio0@2007c000 {\n" + "> +\t\tgpio0: gpio0 at 2007c000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x2007c000 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -464,7 +454,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio1: gpio1@20080000 {\n" + "> +\t\tgpio1: gpio1 at 20080000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x20080000 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -477,7 +467,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio2: gpio2@20084000 {\n" + "> +\t\tgpio2: gpio2 at 20084000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x20084000 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -577,7 +567,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\ti2c1: i2c@20056000 {\n" + "> +\ti2c1: i2c at 20056000 {\n" "> +\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "> +\t\treg = <0x20056000 0x1000>;\n" "> +\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -591,4 +581,4 @@ "> +\t};\n" > +}; -6a60ec516a8c4d18a21605a2d8066afb65aa42227fcfee7d2ae7461b5bb277c4 +1e0ac3e497b66ee01c91a6e7bf053b1bd164230fdb09b323c1aee10e1c40c172
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