From: Like Xu <like.xu.linux@gmail.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Ravi Bangoria <ravi.bangoria@amd.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org, "Bangoria,
Ravikumar" <ravi.bangoria@amd.com>,
Santosh Shukla <santosh.shukla@amd.com>,
"Tom Lendacky (AMD)" <thomas.lendacky@amd.com>,
Ananth Narayan <ananth.narayan@amd.com>
Subject: Re: [PATCH 5/5] KVM: x86/pmu: Hide guest counter updates from the VMRUN instruction
Date: Wed, 19 Apr 2023 21:41:45 +0800 [thread overview]
Message-ID: <34b5dd08-edac-e32f-1884-c8f2b85f7971@gmail.com> (raw)
In-Reply-To: <ZDAvDhV/bpPyt3oX@google.com>
On 7/4/2023 10:56 pm, Sean Christopherson wrote:
> On Fri, Apr 07, 2023, Like Xu wrote:
>> On 7/4/2023 10:18 am, Sean Christopherson wrote:
>>> Wait, really? VMRUN is counted if and only if it enters to a CPL0 guest? Can
>>> someone from AMD confirm this? I was going to say we should just treat this as
>>> "normal" behavior, but counting CPL0 but not CPL>0 is definitely quirky.
>>
>> VMRUN is only counted on a CPL0-target (branch) instruction counter.
>
> Yes or no question: if KVM does VMRUN and a PMC is programmed to count _all_ taken
> branches, will the PMC count VMRUN as a branch if guest CPL>0 according to the VMCB?
YES, my quick tests (based on run_in_user() from KUT on Zen4) show:
EVENTSEL_GUESTONLY + EVENTSEL_ALL + VMRUN_to_USR -> AMD_ZEN_BR_RETIRED + 1
EVENTSEL_GUESTONLY + EVENTSEL_ALL + VMRUN_to_OS -> AMD_ZEN_BR_RETIRED + 1
EVENTSEL_GUESTONLY + EVENTSEL_USR + VMRUN_to_USR -> AMD_ZEN_BR_RETIRED + 1
EVENTSEL_GUESTONLY + EVENTSEL_OS + VMRUN_to_OS -> AMD_ZEN_BR_RETIRED + 1
VENTSEL_GUESTONLY + EVENTSEL_OS + VMRUN_to_USR -> No change
VENTSEL_GUESTONLY + EVENTSEL_USR + VMRUN_to_OS -> No change
I'm actually not surprised and related test would be posted later.
>
>> This issue makes a guest CPL0-target instruction counter inexplicably
>> increase, as if it would have been under-counted before the virtualization
>> instructions were counted.
>
> Heh, it's very much explicable, it's just not desirable, and you and I would argue
> that it's also incorrect.
This is completely inaccurate from the end guest pmu user's perspective.
I have a toy that looks like virtio-pmu, through which guest users can get
hypervisor performance data.
But the side effect of letting the guest see the VMRUN instruction by default is
unacceptable, isn't it ?
>
> AMD folks, are there plans to document this as an erratum? I agree with Like that
> counting VMRUN as a taken branch in guest context is a CPU bug, even if the behavior
> is known/expected.
+CC: Santosh, Tom, Ananth
next prev parent reply other threads:[~2023-04-19 13:42 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-10 10:53 [PATCH 0/5] KVM: x86/pmu: Hide guest counter updates from the VMRUN instruction Like Xu
2023-03-10 10:53 ` [PATCH 1/5] KVM: x86/pmu: Emulate CTR overflow directly in kvm_pmu_handle_event() Like Xu
2023-03-10 10:53 ` [PATCH 2/5] KVM: x86/pmu: Add a helper to check if pmc has PEBS mode enabled Like Xu
2023-05-24 20:54 ` Sean Christopherson
2023-03-10 10:53 ` [PATCH 3/5] KVM: x86/pmu: Move the overflow of a normal counter out of PMI context Like Xu
2023-05-24 21:03 ` Sean Christopherson
2023-03-10 10:53 ` [PATCH 4/5] KVM: x86/pmu: Reorder functions to reduce unnecessary declarations Like Xu
2023-05-24 21:14 ` Sean Christopherson
2023-03-10 10:53 ` [PATCH 5/5] KVM: x86/pmu: Hide guest counter updates from the VMRUN instruction Like Xu
2023-04-07 2:18 ` Sean Christopherson
2023-04-07 8:15 ` Like Xu
2023-04-07 14:56 ` Sean Christopherson
2023-04-19 13:41 ` Like Xu [this message]
2023-04-26 5:25 ` Sandipan Das
2023-04-26 6:25 ` Like Xu
2023-05-24 20:41 ` Sean Christopherson
2023-05-24 20:47 ` Jim Mattson
2023-05-24 21:29 ` Sean Christopherson
2023-05-24 21:32 ` Jim Mattson
2023-05-29 14:51 ` Like Xu
2023-05-30 20:00 ` Jim Mattson
2023-05-24 21:23 ` Sean Christopherson
2023-05-24 21:30 ` Jim Mattson
2023-05-29 14:36 ` Like Xu
2023-03-13 10:57 ` [PATCH 0/5] " Sandipan Das
2023-03-23 8:16 ` Like Xu
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