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From: "Chen, Zide" <zide.chen@intel.com>
To: Sean Christopherson <seanjc@google.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Peter Zijlstra <peterz@infradead.org>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	Jim Mattson <jmattson@google.com>,
	Mingwei Zhang <mizhang@google.com>,
	Das Sandipan <Sandipan.Das@amd.com>,
	Shukla Manali <Manali.Shukla@amd.com>,
	Dapeng Mi <dapeng1.mi@linux.intel.com>,
	Falcon Thomas <thomas.falcon@intel.com>,
	Xudong Hao <xudong.hao@intel.com>
Subject: Re: [PATCH 13/15] KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is not set
Date: Mon, 3 Aug 2026 16:32:38 -0500	[thread overview]
Message-ID: <34cce79f-e4e2-4d08-bc80-f87da001f573@intel.com> (raw)
In-Reply-To: <20260707183405.15571-14-zide.chen@intel.com>



On 7/7/2026 1:34 PM, Zide Chen wrote:
> Intel PerfMon v5 introduces the ANYTHREAD_DEPRECATION capability
> (CPUID.0AH:EDX[15]) to indicate that AnyThread counting is deprecated
> and that writes to the AnyThread bit in IA32_PERFEVTSELx are ignored.
> 
> When ANYTHREAD_DEPRECATION is present in the guest CPUID, emulate the
> architectural behavior and silently ignore writes to the AnyThread bit
> instead of injecting #GP.
> 
> Continue to inject #GP when ANYTHREAD_DEPRECATION is not present in the
> guest CPUID, e.g. for PerfMon v3/v4 guests or when the capability is
> not configured for a PerfMon v5+ guest.

Advertise CPUID.0AH:EDX[15] only for PMU version 5+ guests, since the
bit doesn't exist below version 5.

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 7fa5d6d51fe9..2dcce8119f1c 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1542,7 +1542,7 @@ static inline int __do_cpuid_func(struct
kvm_cpuid_array *array, u32 function)
                                            KVM_MAX_NR_FIXED_COUNTERS);
                edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;

-               if (kvm_pmu_cap.version)
+               if (kvm_pmu_cap.version >= 5)
                        edx.split.anythread_deprecated = 1;

                entry->eax = eax.full;

> Signed-off-by: Zide Chen <zide.chen@intel.com>
> ---
>  arch/x86/kvm/vmx/pmu_intel.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index 3f41e4916986..2c2a54ac55ad 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -508,6 +508,11 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  			if (data & eventsel_rsvd)
>  				return 1;
>  
> +			/*
> +			 * On PerfMon v5+, KVM may allow writes to the AnyThread
> +			 * bit and silently discard them.
> +			 */
> +			data &= ~ARCH_PERFMON_EVENTSEL_ANY;
>  			if (data != pmc->eventsel) {
>  				pmc->eventsel = data;
>  				pmc->eventsel_hw = data;
> @@ -627,6 +632,9 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
>  	pmu->all_valid_pmc_mask64 = (BIT_ULL(nr_gp_counters) - 1) &
>  				    kvm_pmu_cap.cntr_mask64;
>  
> +	if (pmu->version >= 5 && edx.split.anythread_deprecated)
> +		pmu->eventsel_rsvd &= ~ARCH_PERFMON_EVENTSEL_ANY;
> +
>  	entry = kvm_find_cpuid_entry_index(vcpu, 7, 0);
>  	if (entry &&
>  	    (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&


  reply	other threads:[~2026-08-03 21:32 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-07 18:33 [PATCH 00/15] KVM: x86/pmu: Add mediated vPMU PerfMon v5 support Zide Chen
2026-07-07 18:33 ` [PATCH 01/15] KVM: x86/pmu: Remove redundant Perf Global Status MSR bit definitions Zide Chen
2026-07-07 18:33 ` [PATCH 02/15] KVM: x86/pmu: Rename all_valid_pmc_idx to all_valid_pmc_mask Zide Chen
2026-07-28 19:11   ` Sean Christopherson
2026-07-28 19:51     ` Chen, Zide
2026-07-07 18:33 ` [PATCH 03/15] KVM: x86/pmu: Rename reserved_bits to eventsel_rsvd in kvm_pmu Zide Chen
2026-07-07 18:33 ` [PATCH 04/15] KVM: x86/pmu: Add PMC bitmap accessor helpers Zide Chen
2026-07-28 19:28   ` Sean Christopherson
2026-07-28 20:42     ` Chen, Zide
2026-07-28 23:35       ` Sean Christopherson
2026-07-07 18:33 ` [PATCH 05/15] KVM: x86/pmu: Drop nr_arch_{gp,fixed}_counters from kvm_pmu Zide Chen
2026-07-07 18:33 ` [PATCH 06/15] KVM: x86/pmu: Expose kvm_host_pmu to vendor modules Zide Chen
2026-07-07 18:33 ` [PATCH 07/15] perf/x86: Plumb counter bitmap from x86_pmu to x86_pmu_cap Zide Chen
2026-07-07 18:33 ` [PATCH 08/15] KVM: x86/pmu: Switch to bitmask-based KVM PMU capabilities Zide Chen
2026-07-23 21:47   ` Jim Mattson
2026-07-24 15:15     ` Chen, Zide
2026-07-07 18:33 ` [PATCH 09/15] perf/x86: Remove num_counters_{gp,fixed} from x86_pmu_capability Zide Chen
2026-07-23 21:49   ` Jim Mattson
2026-07-24 15:52     ` Chen, Zide
2026-07-07 18:34 ` [PATCH 10/15] KVM: x86/pmu: Emulate the GLOBAL_STATUS_SET and GLOBAL_INUSE MSRs Zide Chen
2026-08-03 20:37   ` Chen, Zide
2026-07-07 18:34 ` [PATCH 11/15] KVM: x86/pmu: Emulate streamlined Freeze-LBR-on-PMI Zide Chen
2026-07-28 19:33   ` Sean Christopherson
2026-07-28 19:48     ` Chen, Zide
2026-07-07 18:34 ` [PATCH 12/15] KVM: x86/pmu: Populate CPUID.0AH:ECX fixed-counter bitmap Zide Chen
2026-07-07 18:34 ` [PATCH 13/15] KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is not set Zide Chen
2026-08-03 21:32   ` Chen, Zide [this message]
2026-07-07 18:34 ` [PATCH 14/15] KVM: x86/pmu: Advertise PerfMon version 5 on Intel hosts Zide Chen
2026-07-23 21:53   ` Jim Mattson
2026-07-23 23:25     ` Chen, Zide
2026-07-24  3:20       ` Jim Mattson
2026-07-24 14:19         ` Chen, Zide
2026-07-30  3:30           ` Mi, Dapeng
2026-07-07 18:34 ` [PATCH 15/15] KVM: selftests: Support fixed counters bitmap in pmu_counters_test Zide Chen

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