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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd42c5880sm40810155e9.19.2025.03.05.23.47.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Mar 2025 23:47:39 -0800 (PST) Message-ID: <34ea7324-2df6-4c97-97d3-b37463a3ff7b@linaro.org> Date: Thu, 6 Mar 2025 08:47:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h' To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei References: <20250206181827.41557-1-philmd@linaro.org> <20250206181827.41557-3-philmd@linaro.org> <1faf3550-909d-47ba-89e5-c8955a03784e@redhat.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <1faf3550-909d-47ba-89e5-c8955a03784e@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 9/2/25 08:34, Paolo Bonzini wrote: > On 2/6/25 19:18, Philippe Mathieu-Daudé wrote: >> "cpu.h" is target-specific. Definitions which can be used >> by hw/ code when building QOM blocks can be in "cpu-qom.h", >> which is target-agnostic. >> >> Move the MISA bits (removing the pointless target_ulong cast) >> and the IRQ index definitions. > > This seems wrong.  Why not move from cpu.h to cpu_bits.h, and include that? Because of ... > > Paolo > >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   target/riscv/cpu-qom.h  | 40 ++++++++++++++++++++++++++++++++++++++++ >>   target/riscv/cpu.h      | 24 ------------------------ >>   target/riscv/cpu_bits.h | 15 --------------- >>   3 files changed, 40 insertions(+), 39 deletions(-) >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index f97c48a3943..80701bc77fe 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -720,21 +720,6 @@ typedef enum RISCVException { >>   #define RISCV_EXCP_INT_FLAG                0x80000000 >>   #define RISCV_EXCP_INT_MASK                0x7fffffff >> -/* Interrupt causes */ >> -#define IRQ_U_SOFT                         0 >> -#define IRQ_S_SOFT                         1 >> -#define IRQ_VS_SOFT                        2 >> -#define IRQ_M_SOFT                         3 >> -#define IRQ_U_TIMER                        4 >> -#define IRQ_S_TIMER                        5 >> -#define IRQ_VS_TIMER                       6 >> -#define IRQ_M_TIMER                        7 >> -#define IRQ_U_EXT                          8 >> -#define IRQ_S_EXT                          9 >> -#define IRQ_VS_EXT                         10 >> -#define IRQ_M_EXT                          11 >> -#define IRQ_S_GEXT                         12 >> -#define IRQ_PMU_OVF                        13 >>   #define IRQ_LOCAL_MAX                      64 >>   /* -1 is due to bit zero of hgeip and hgeie being ROZ. */ >>   #define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1) ... this TARGET_LONG_BITS use in cpu_bits.h. and: target/riscv/cpu_bits.h:1070:44: error: attempt to use a poisoned identifier 1070 | #define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0 | ^ But I got your idea and will only move these 2 to "cpu.h".