From: Krzysztof Kozlowski <krzk@kernel.org>
To: "Thierry Reding" <thierry.reding@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>
Cc: Jon Hunter <jonathanh@nvidia.com>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
Date: Thu, 19 Mar 2026 17:11:17 +0100 [thread overview]
Message-ID: <353939e0-ef52-4c8f-bf71-ff27fa2c7d7a@kernel.org> (raw)
In-Reply-To: <20260319160110.2131954-4-thierry.reding@kernel.org>
On 19/03/2026 17:01, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The six PCIe controllers found on Tegra264 are of two types: one is used
> for the internal GPU and therefore is not connected to a UPHY and the
> remaining five controllers are typically routed to a PCI slot and have
> additional controls for the physical link.
>
> While these controllers can be switched into endpoint mode, this binding
> describes the root complex mode only.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++
> 1 file changed, 92 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> new file mode 100644
> index 000000000000..56d69de2788b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra264 PCIe controller
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> +
> +properties:
> + compatible:
> + const: nvidia,tegra264-pcie
> +
> + reg:
> + minItems: 4
> + maxItems: 5
> +
> + reg-names:
> + minItems: 4
> + maxItems: 5
> +
> + interrupts:
> + minItems: 1
> + maxItems: 4
> +
> + dma-coherent: true
> +
> + nvidia,bpmp:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + Must contain a pair of phandle (to the BPMP controller node) and
> + controller ID. The following are the controller IDs for each controller:
> +
> + 0: C0
> + 1: C1
> + 2: C2
> + 3: C3
> + 4: C4
> + 5: C5
> + items:
> + - items:
> + - description: phandle to the BPMP controller node
> + - description: PCIe controller ID
> + maximum: 5
> +
> +unevaluatedProperties: false
This goes before example
> +
> +required:
> + - interrupt-map
> + - interrupt-map-mask
> + - iommu-map
> + - msi-map
> + - nvidia,bpmp
> +
> +allOf:
> + - $ref: /schemas/pci/pci-host-bridge.yaml#
> + - oneOf:
> + - description: C0 controller (no UPHY)
It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.
> + properties:
> + reg:
> + items:
> + - description: application layer registers
> + - description: transaction layer registers
> + - description: privileged transaction layer registers
> + - description: ECAM-compatible configuration space
> +
> + reg-names:
> + items:
> + - const: xal
> + - const: xtl
> + - const: xtl-pri
> + - const: ecam
> +
> + - description: C1-C5 controllers (with UPHY)
> + properties:
> + reg:
> + items:
> + - description: application layer registers
> + - description: transaction layer registers
> + - description: privileged transaction layer registers
> + - description: data link/physical layer registers
> + - description: ECAM-compatible configuration space
> +
> + items:
> + - const: xal
> + - const: xtl
> + - const: xtl-pri
> + - const: xpl
> + - const: ecam
All of above are part of top level.
And speaking about example - where is it? How can you then test (verify)
this?
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-03-19 16:11 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-19 16:01 [PATCH 0/5] PCI: tegra: Add Tegra264 support Thierry Reding
2026-03-19 16:01 ` [PATCH 1/5] soc/tegra: Update BPMP ABI header Thierry Reding
2026-03-19 16:15 ` Krzysztof Kozlowski
2026-03-20 9:34 ` Thierry Reding
2026-03-20 9:44 ` Krzysztof Kozlowski
2026-03-20 9:49 ` Krzysztof Kozlowski
2026-03-20 10:52 ` Thierry Reding
2026-03-20 12:46 ` Krzysztof Kozlowski
2026-03-19 16:01 ` [PATCH 2/5] firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function Thierry Reding
2026-03-19 16:01 ` [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Thierry Reding
2026-03-19 16:11 ` Krzysztof Kozlowski [this message]
2026-03-20 10:56 ` Thierry Reding
2026-03-19 17:53 ` Rob Herring (Arm)
2026-03-19 21:26 ` Rob Herring
2026-03-20 9:39 ` Thierry Reding
2026-03-20 13:06 ` Rob Herring
2026-03-20 13:48 ` Thierry Reding
2026-03-20 15:58 ` Rob Herring
2026-03-19 16:01 ` [PATCH 4/5] PCI: tegra: Add Tegra264 support Thierry Reding
2026-03-19 16:14 ` Krzysztof Kozlowski
2026-03-20 10:39 ` Thierry Reding
2026-03-19 17:46 ` Bjorn Helgaas
2026-03-20 10:34 ` Thierry Reding
2026-03-20 14:27 ` Bjorn Helgaas
2026-03-19 16:01 ` [PATCH 5/5] arm64: tegra: Add PCI controllers on Tegra264 Thierry Reding
-- strict thread matches above, loose matches on Subject: below --
2026-03-20 6:14 [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller kernel test robot
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