Re: [PATCH] clk: renesas: cpg-mssr: Read back reset registers to assure values latched

[Marek Vasut <marek.vasut@mailbox.org>]

On 9/18/25 1:11 PM, Lad, Prabhakar wrote:

Hello Prabhakar,

>> diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
>> index 65dfaceea71f..7b52e8235984 100644
>> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
>> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
>> @@ -688,6 +688,7 @@ static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
>>
>>          /* Reset module */
>>          writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]);
>> +       readl(priv->pub.base0 + priv->reset_regs[reg]);
> Fyi on the RZ/T2H and RZ/N2H SoCs which uses the same driver we need
> to read the reset register `7` times and confirm [0] (as mentioned in
> the HW manual). So after reading do we want to confirm the bit is
> set/clear?
This is interesting, I wonder if the readback is something more common 
to this reset controller.

Why 7 times ? Is this documented in one of the HW manuals ? Are those 
public and can you share a link to them , with the specific chapter or 
page I should read about this 7 times read requirement ?