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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2/7/25 11:01 PM, Andrew Cooper wrote: > One bugfix, and two minor patches to get UBSAN working with RISCV. They > should be considered for 4.20 at this juncture. Considering that RISC-V port isn't really usable and changes are quite straightforward and low risk: Release-Acked-By: Oleksii Kurochko Thanks. ~ Oleksii > > I tried to get this working everywhere, but: > > 1) ARM32 has some problem with dump_execution_state() and dies with an > undefined instruction error. > > 2) PPC doesn't get any console output, and also appears to have no exception > handling either. Also, when it doesn't succeed, it takes ages to fail. > > Andrew Cooper (3): > RISCV/boot: Run constructors during setup > RISCV/asm: Use CALL rather than JAL > RISCV: Activate UBSAN in testing > > automation/gitlab-ci/build.yaml | 3 +++ > xen/arch/riscv/Kconfig | 1 + > xen/arch/riscv/entry.S | 2 +- > xen/arch/riscv/include/asm/processor.h | 2 ++ > xen/arch/riscv/riscv64/head.S | 12 ++++++------ > xen/arch/riscv/setup.c | 2 ++ > xen/arch/riscv/traps.c | 2 +- > xen/common/ubsan/ubsan.c | 5 ++++- > 8 files changed, 20 insertions(+), 9 deletions(-) > --------------VNeXBlzjFKD04pG7X6VhbF4D Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit


On 2/7/25 11:01 PM, Andrew Cooper wrote:
One bugfix, and two minor patches to get UBSAN working with RISCV.  They
should be considered for 4.20 at this juncture.
Considering that RISC-V port isn't really usable and changes are quite straightforward
and low risk:
 Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Thanks.

~ Oleksii

I tried to get this working everywhere, but:

1) ARM32 has some problem with dump_execution_state() and dies with an
   undefined instruction error.

2) PPC doesn't get any console output, and also appears to have no exception
   handling either.  Also, when it doesn't succeed, it takes ages to fail.

Andrew Cooper (3):
  RISCV/boot: Run constructors during setup
  RISCV/asm: Use CALL rather than JAL
  RISCV: Activate UBSAN in testing

 automation/gitlab-ci/build.yaml        |  3 +++
 xen/arch/riscv/Kconfig                 |  1 +
 xen/arch/riscv/entry.S                 |  2 +-
 xen/arch/riscv/include/asm/processor.h |  2 ++
 xen/arch/riscv/riscv64/head.S          | 12 ++++++------
 xen/arch/riscv/setup.c                 |  2 ++
 xen/arch/riscv/traps.c                 |  2 +-
 xen/common/ubsan/ubsan.c               |  5 ++++-
 8 files changed, 20 insertions(+), 9 deletions(-)
--------------VNeXBlzjFKD04pG7X6VhbF4D--