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Mon, 27 Jun 2022 13:31:30 +0000 (GMT) Received: from [9.145.155.49] (unknown [9.145.155.49]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 27 Jun 2022 13:31:30 +0000 (GMT) Message-ID: <35c562e1-cdcd-41ce-1957-bd35c72a78ca@linux.ibm.com> Date: Mon, 27 Jun 2022 15:31:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Content-Language: en-US To: Pierre Morel , qemu-s390x@nongnu.org Cc: qemu-devel@nongnu.org, borntraeger@de.ibm.com, pasic@linux.ibm.com, richard.henderson@linaro.org, david@redhat.com, thuth@redhat.com, cohuck@redhat.com, mst@redhat.com, pbonzini@redhat.com, kvm@vger.kernel.org, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, eblake@redhat.com, armbru@redhat.com, seiden@linux.ibm.com, nrb@linux.ibm.com References: <20220620140352.39398-1-pmorel@linux.ibm.com> <20220620140352.39398-3-pmorel@linux.ibm.com> From: Janosch Frank Subject: Re: [PATCH v8 02/12] s390x/cpu_topology: CPU topology objects and structures In-Reply-To: <20220620140352.39398-3-pmorel@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: D1KJHIDtUJvBVhdSZQpohxyC-g9sDkuF X-Proofpoint-ORIG-GUID: W0rMNabKiycDDEVU9OA33bxtbJEncRxn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-06-27_06,2022-06-24_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 phishscore=0 adultscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 priorityscore=1501 clxscore=1011 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206270059 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 6/20/22 16:03, Pierre Morel wrote: > We use new objects to have a dynamic administration of the CPU topology. > The highest level object in this implementation is the s390 book and > in this first implementation of CPU topology for S390 we have a single > book. > The book is built as a SYSBUS bridge during the CPU initialization. > Other objects, sockets and core will be built after the parsing > of the QEMU -smp argument. > > Every object under this single book will be build dynamically > immediately after a CPU has be realized if it is needed. > The CPU will fill the sockets once after the other, according to the > number of core per socket defined during the smp parsing. > > Each CPU inside a socket will be represented by a bit in a 64bit > unsigned long. Set on plug and clear on unplug of a CPU. > > For the S390 CPU topology, thread and cores are merged into > topology cores and the number of topology cores is the multiplication > of cores by the numbers of threads. > > Signed-off-by: Pierre Morel [...] > diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h > index 7d6d01325b..216adfde26 100644 > --- a/target/s390x/cpu.h > +++ b/target/s390x/cpu.h > @@ -565,6 +565,53 @@ typedef union SysIB { > } SysIB; > QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); > > +/* CPU type Topology List Entry */ > +typedef struct SysIBTl_cpu { > + uint8_t nl; > + uint8_t reserved0[3]; > + uint8_t reserved1:5; > + uint8_t dedicated:1; > + uint8_t polarity:2; > + uint8_t type; > + uint16_t origin; > + uint64_t mask; > +} SysIBTl_cpu; > +QEMU_BUILD_BUG_ON(sizeof(SysIBTl_cpu) != 16); > + > +/* Container type Topology List Entry */ > +typedef struct SysIBTl_container { > + uint8_t nl; > + uint8_t reserved[6]; > + uint8_t id; > +} QEMU_PACKED SysIBTl_container; > +QEMU_BUILD_BUG_ON(sizeof(SysIBTl_container) != 8); > + > +/* Generic Topology List Entry */ > +typedef union SysIBTl_entry { > + uint8_t nl; This union member is unused, isn't it? > + SysIBTl_container container; > + SysIBTl_cpu cpu; > +} SysIBTl_entry; > + > +#define TOPOLOGY_NR_MAG 6 TOPOLOGY_TOTAL_NR_MAGS ? > +#define TOPOLOGY_NR_MAG6 0 TOPOLOGY_NR_TLES_MAG6 ? I'm open to other suggestions but we need to differentiate between the number of mag array entries and the number of TLEs in the MAGs. > +#define TOPOLOGY_NR_MAG5 1 > +#define TOPOLOGY_NR_MAG4 2 > +#define TOPOLOGY_NR_MAG3 3 > +#define TOPOLOGY_NR_MAG2 4 > +#define TOPOLOGY_NR_MAG1 5 I'd appreciate a \n here. > +/* Configuration topology */ > +typedef struct SysIB_151x { > + uint8_t res0[2]; You're using "reserved" everywhere but now it's "rev"? > + uint16_t length; > + uint8_t mag[TOPOLOGY_NR_MAG]; > + uint8_t res1; > + uint8_t mnest; > + uint32_t res2; > + SysIBTl_entry tle[0]; > +} SysIB_151x; > +QEMU_BUILD_BUG_ON(sizeof(SysIB_151x) != 16); > + > /* MMU defines */ > #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ > #define ASCE_SUBSPACE 0x200 /* subspace group control */