diff for duplicates of <3665319.WRLLeiHAYk@avalon> diff --git a/a/1.txt b/N1/1.txt index effcb33..3d883f1 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -10,7 +10,7 @@ On Thursday 27 November 2014 11:51:16 Will Deacon wrote: > long-descriptor page tables. 4k, 16k and 64k pages are supported, with > up to 4-levels of walk to cover a 48-bit address space. > -> Signed-off-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> +> Signed-off-by: Will Deacon <will.deacon@arm.com> > --- > MAINTAINERS | 1 + > drivers/iommu/Kconfig | 9 + @@ -25,14 +25,14 @@ On Thursday 27 November 2014 11:51:16 Will Deacon wrote: > index 0ff630de8a6d..d3ca31b7c960 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS -> @@ -1562,6 +1562,7 @@ M: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> -> L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers) +> @@ -1562,6 +1562,7 @@ M: Will Deacon <will.deacon@arm.com> +> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) > S: Maintained > F: drivers/iommu/arm-smmu.c > +F: drivers/iommu/io-pgtable-arm.c > > ARM64 PORT (AARCH64 ARCHITECTURE) -> M: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> +> M: Catalin Marinas <catalin.marinas@arm.com> > diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig > index 0f10554e7114..e1742a0146f8 100644 > --- a/drivers/iommu/Kconfig @@ -88,7 +88,7 @@ On Thursday 27 November 2014 11:51:16 Will Deacon wrote: > + * > + * Copyright (C) 2014 ARM Limited > + * -> + * Author: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> +> + * Author: Will Deacon <will.deacon@arm.com> > + */ > + > +#define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt @@ -343,7 +343,7 @@ On Thursday 27 November 2014 11:51:16 Will Deacon wrote: > + << ARM_LPAE_PTE_ATTRINDX_SHIFT); In my case I'll need to manage the NS bit (here and when allocating tables in -__arm_lpae_map). The exact requirements are not exactly clear at the moment +__arm_lpae_map). The exact requirements are not exactly clear@the moment I'm afraid, the datasheet doesn't clearly document secure behaviour, but tests showed that setting the NS was necessary. diff --git a/a/content_digest b/N1/content_digest index 9bbce05..891c1da 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,15 +1,9 @@ "ref\01417089078-22900-1-git-send-email-will.deacon@arm.com\0" "ref\01417089078-22900-3-git-send-email-will.deacon@arm.com\0" - "ref\01417089078-22900-3-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org\0" - "From\0Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>\0" - "Subject\0Re: [PATCH 2/4] iommu: add ARM LPAE page table allocator\0" + "From\0laurent.pinchart@ideasonboard.com (Laurent Pinchart)\0" + "Subject\0[PATCH 2/4] iommu: add ARM LPAE page table allocator\0" "Date\0Mon, 01 Dec 2014 01:29:46 +0200\0" - "To\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0" - "Cc\0iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" - Varun.Sethi-KZfg59tc24xl57MIdRCFDg@public.gmane.org - prem.mallappa-dY08KVG/lbpWk0Htik3J/w@public.gmane.org - Robin.Murphy-5wv7dgnIgG8@public.gmane.org - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Will,\n" @@ -24,7 +18,7 @@ "> long-descriptor page tables. 4k, 16k and 64k pages are supported, with\n" "> up to 4-levels of walk to cover a 48-bit address space.\n" "> \n" - "> Signed-off-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\n" + "> Signed-off-by: Will Deacon <will.deacon@arm.com>\n" "> ---\n" "> MAINTAINERS | 1 +\n" "> drivers/iommu/Kconfig | 9 +\n" @@ -39,14 +33,14 @@ "> index 0ff630de8a6d..d3ca31b7c960 100644\n" "> --- a/MAINTAINERS\n" "> +++ b/MAINTAINERS\n" - "> @@ -1562,6 +1562,7 @@ M:\tWill Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\n" - "> L:\tlinux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers)\n" + "> @@ -1562,6 +1562,7 @@ M:\tWill Deacon <will.deacon@arm.com>\n" + "> L:\tlinux-arm-kernel at lists.infradead.org (moderated for non-subscribers)\n" "> S:\tMaintained\n" "> F:\tdrivers/iommu/arm-smmu.c\n" "> +F:\tdrivers/iommu/io-pgtable-arm.c\n" "> \n" "> ARM64 PORT (AARCH64 ARCHITECTURE)\n" - "> M:\tCatalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>\n" + "> M:\tCatalin Marinas <catalin.marinas@arm.com>\n" "> diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig\n" "> index 0f10554e7114..e1742a0146f8 100644\n" "> --- a/drivers/iommu/Kconfig\n" @@ -102,7 +96,7 @@ "> + *\n" "> + * Copyright (C) 2014 ARM Limited\n" "> + *\n" - "> + * Author: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\n" + "> + * Author: Will Deacon <will.deacon@arm.com>\n" "> + */\n" "> +\n" "> +#define pr_fmt(fmt)\t\"arm-lpae io-pgtable: \" fmt\n" @@ -357,7 +351,7 @@ "> +\t\t\t\t<< ARM_LPAE_PTE_ATTRINDX_SHIFT);\n" "\n" "In my case I'll need to manage the NS bit (here and when allocating tables in \n" - "__arm_lpae_map). The exact requirements are not exactly clear at the moment \n" + "__arm_lpae_map). The exact requirements are not exactly clear@the moment \n" "I'm afraid, the datasheet doesn't clearly document secure behaviour, but tests \n" "showed that setting the NS was necessary.\n" "\n" @@ -892,4 +886,4 @@ "\n" Laurent Pinchart -533e586bd5939f0a521dfc024edab1f0e6f92cd8ba086f968ec79f493ad92748 +b2625950c66cd243dbc0547d9093875e32fb95823df8ae4be969962215e8508c
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