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a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787880087; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:content-language:in-reply-to:references; bh=yoP6VEGX2qKT4fJJ41ckjTBIoHRo/cpY0rQo5BL3F5M=; b=DT/+e5373uCTY88e5m6Jl2JmLZLvIcsFMu26DVl8YUhvnkLu+0YGy5VBGBnHUrGyPhvS1o zMfrPXoRf0AyX4TGu0eewj+4ICht3H025FAmNn1CUFP+r5f6Zfd2Pk6j4RucPoqOkv2EkJ OjiVFOIyI8G19+MddnBABh7sYRprFMTaDWVSqZVGg7fLO1C5W/SyE0JXNopuKDLzjfKs2o G7ReKAOCtNm3FVauiVo33JuBLNydzVTEdLJ2RhSN1yJbLFOHU6WYRa/B0A0degUKh1g0tq lBIyIswX0kyXL8a6V21i7+l6boIa0PvXRFlJmefquKPYtJFEa5bTUhuGRu/foA== Message-ID: <36740ee5-9cac-4bd4-a67a-3ab5cffe9691@nabladev.com> Date: Thu, 27 Aug 2026 19:06:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/4] ddr: imx: Allow to call ddr init without logging failure To: Frieder Schrempf , Frieder Schrempf , Stefano Babic , Fabio Estevam , Ilias Apalodimas , Tom Rini , u-boot@lists.u-boot-project.org Cc: uboot-imx@nxp.com, Simona Toaca , Viorel Suman References: <20260819070758.51350-1-frieder@fris.de> <20260819070758.51350-3-frieder@fris.de> <83ee9efb-e09f-45d8-ac0a-cd9b2797c513@nabladev.com> <59ed6576-06dd-42bf-8ea2-18de427955a4@kontron.de> <5ef02e5a-c0ac-4afb-b90d-4d6d075b05e6@kontron.de> Content-Language: en-US From: Marek Vasut In-Reply-To: <5ef02e5a-c0ac-4afb-b90d-4d6d075b05e6@kontron.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org On 8/27/26 3:35 PM, Frieder Schrempf wrote: > On 26.08.26 14:24, Marek Vasut wrote: >> On 8/26/26 10:12 AM, Frieder Schrempf wrote: >> >> [...] >> >>>>> I'm not sure, but even if it would work, it would require several >>>>> separate init attempts only to read the IDs >>>> >>>> Why ? Init the bus in slowest mode with widest bus settings, then try >>>> MRRD on all available DRAM chips, then figure out which ones report >>>> valid IDs and which ones fail the MRd . >>> >>> As far as I can see this doesn't work. If we use the widest bus setting >>> (CsPresent=0x3) on a single rank module, the training fails and the DDR >>> remains in a state where the MR read doesn't work yet. >> >> Do you need training to read the IDs ? Simply force-use the slowest bus >> mode (100 MTps iirc), the training is only relevant for the high-speed >> modes. > I don't see any existing code path for any i.MX with DDR4 that doesn't > do the training before accessing MR registers. Do you have any > references or examples? Do you have any sources for the claim that the > training is only relevant for the high-speed modes? I couldn't find > anything that supports this. What happens if you simply skip the DDR training, return 0 from ddr_cfg_phy() ? > Also I would assume that doing the MRRD on an unused CS would give me > back some arbitrary random values. While I could interpret an unknown > value as "rank/cs not present", I don't think its reliable enough. Or do > you know of any error condition being reported for failed MRRD? Try it and see what happens ?